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december 2008 208012 -01 1/98 1 m29w256gh m29w256gl 256-mbit (32 mbit x8 or 16 mbit x16, page, uniform block) 3 v supply flash memory features ? supply voltage ?v cc = 2.7 to 3.6 v for program, erase, read ?v ccq = 1.65 to 3.6 v for i/o buffers ?v pph = 12 v for fast program (optional) ? asynchronous random/page read ? page size: 8 words or 16 bytes ? page access: 25, 30 ns ? random access: 60 (only available upon customer request) or 70, 80 ns ? fast program commands ? 32 words (64-byte write buffer) ? enhanced buffered program commands ? 256 words ? programming time ?16 s per byte/word typical ? chip program time: 10 s with v pph and 16 s without v pph ? memory organization ? m29256gh/l: 256 main blocks, 128 kbytes/64 kwords each ? program/erase controller ? embedded byte/word program algorithms ? program/ erase suspend and resume ? read from any block during program suspend ? read and program another block during erase suspend ? unlock bypass/block erase/chip erase/write to buffer/enhanced buffer program commands ? faster production/batch programming ? faster block and chip erase ? v pp /wp pin for fast program and write: protects first or last block regardless of block protection settings ? software protection: ? volatile protection ? non-volatile protection ? password protection ? common flash interface ? 64-bit security code ? 128-word extended memory block ? extra block used as security block or to store additional information ? low power consumption ? standby and automatic standby ? minimum 100,000 program/erase cycles per block ? rohs compliant packages ? automotive device grade: temperature -40 c to 85 c (automotive grade certified) bga tsop56 (n) 14 x 20 mm lbga (zs) 11 x 13 mm bga tbga64 (za) 10 x 13 mm table 1. device summary root part number device code m29w256gh / m29w256gl 227eh + 2222h + 2201 www.numonyx.com
contents m29w256gh, m29w256gl 2/98 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 address inputs (a0-a23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 data inputs/outputs (dq0-dq7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 data inputs/outputs (dq8-dq14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 data inputs/outputs or address inputs (dq15a-1) . . . . . . . . . . . . . . . . . . 12 2.5 chip enable (e ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6 output enable (g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.7 write enable (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.8 v pp /write protect (v pp/ wp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.9 reset (rp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.10 ready/busy output (rb ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.11 byte/word organization select (byte ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.12 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.13 v ccq input/output supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.14 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 automatic standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7 auto select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7.1 read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7.2 verify extended memory block protection indicator . . . . . . . . . . . . . . . . 18 3.7.3 verify block protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7.4 hardware block protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
m29w256gh, m29w256gl contents 3/98 5 software protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 volatile protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 non-volatile protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.1 non-volatile protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.2 non-volatile protection bit lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 password protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.1 extended block protection bit (dq0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.2 non-volatile protection mode lock bit (dq1) . . . . . . . . . . . . . . . . . . . . . 26 5.4.3 password protection mode lock bit (dq2) . . . . . . . . . . . . . . . . . . . . . . . 26 5.4.4 dq15 to dq3 reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1.1 read/reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1.2 auto select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1.3 read cfi query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1.4 chip erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1.5 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1.6 erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1.7 erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1.8 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1.9 program suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.10 program resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2 unlock bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.1 unlock bypass program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.2 unlock bypass block erase command . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.3 unlock bypass chip erase command . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2.4 unlock bypass write to buffer program command . . . . . . . . . . . . . . . . 36 6.2.5 unlock bypass reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . fast program commands 37 6.3.1 write to buffer program command set . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3.2 . . . . . . . . . . . . . . . . . . . . . enhanced buffered program command set 40 6.4 protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.4.1 lock register command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . extended memory block 43
contents m29w256gh, m29w256gl 4/98 6.4.3 volatile protection mode command set . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.4.4 non-volatile protection mode command set . . . . . . . . . . . . . . . . . . . . . 45 6.4.5 nvpb lock bit command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.4.6 password protection mode command set . . . . . . . . . . . . . . . . . . . . . . . 47 6.4.7 exit protection command set command . . . . . . . . . . . . . . . . . . . . . . . . 48 7 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.1 data polling bit (dq7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.2 toggle bit (dq6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.3 error bit (dq5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.4 erase timer bit (dq3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.5 alternative toggle bit (dq2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.6 buffered program abort bit (dq1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 appendix a block addresses and read/modify protection groups . . . . . . . . . . 78 appendix b common flash interface (cfi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 appendix c extended memory block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 c.1 factory locked extended memory block . . . . . . . . . . . . . . . . . . . . . . . . . . 91 c.2 customer lockable extended memory block . . . . . . . . . . . . . . . . . . . . . . . 92 appendix d flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
m29w256gh, m29w256gl list of tables 5/98 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. v pp /wp functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. bus operations, 8-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. bus operations, 16-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. read electronic signature - auto select mode - programmer method (8-bit mode) . . . . . . 20 table 7. read electronic signature - auto select mode - programmer method (16-bit mode) . . . . . 20 table 8. block protection - auto select mode - programmer method (8-bit mode) . . . . . . . . . . . . . . 21 table 9. block protection - auto select mode - programmer method (16-bit mode) . . . . . . . . . . . . . 21 table 10. lock register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11. block protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12. standard commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. standard commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 table 14. unlock bypass commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 15. unlock bypass commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 16. write to buffer commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9 table 17. write to buffer commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 18. enhanced buffered program commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 19. block protection commands, 8-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 20. block protection commands, 16-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 21. program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . 52 table 22. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 23. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 24. operating and ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 25. power-up waiting timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 26. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 27. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 28. read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 29. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 30. write ac characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 31. reset ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 32. accelerated program and data polling/data toggle ac characteristics . . . . . . . . . . . . . . . . 73 table 33. tsop56 ? 56 lead plastic thin small outline, 14 x 20 mm, package mechanical data . . . . 74 table 34. tbga64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package mechanical data. . . . 75 table 35. lbga64 11 x 13 mm?8 x 8 active ball array, 1 mm pitch, package mechanical data. . . . 76 table 36. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 37. block addresses 0 - 127 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 38. block addresses 128 - 255 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 39. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 40. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 41. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 table 42. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 43. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 44. security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 45. extended memory block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 46. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
list of figures m29w256gh, m29w256gl 6/98 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. tsop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. tbga and lbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. software protection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 6. lock register program flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 7. nvpb program/erase algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 8. data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 9. data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 10. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 11. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 12. power-up waiting timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 13. random read ac waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 14. random read ac waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 15. page read ac waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 16. write enable controlled program waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 17. write enable controlled program waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 18. chip enable controlled program waveforms (8-bit mode). . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 19. chip enable controlled program waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 20. chip/block erase waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 21. reset ac waveforms (no program/erase ongoing). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 22. reset during program/erase operation ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 23. accelerated program timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 24. data polling ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 25. toggle/alternative toggle bit polling ac waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . 73 figure 26. tsop56 ? 56 lead plastic thin small outline, 14 x 20 mm, package outline . . . . . . . . . . . . 74 figure 27. tbga64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package outline . . . . . . . . . . . 75 figure 28. lbga64 11 x 13 mm?8 x 8 active ball array, 1 mm pitch, package outline . . . . . . . . . . . 76 figure 29. write to buffer program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 30. enhanced buffered program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 94
m29w256gh, m29w256gl description 7/98 1 description the m29w256gh and m29w256gl are 256-mbit (16 mbit x16 or 32 mbit x8) non-volatile flash memories that can be read, erased and reprogrammed. these operations can be performed using a single low voltage (2.7 to 3.6 v) supply. on power-up the memory defaults to its read mode. the memory array is divided into 64-kword/128-kbyte uniform blocks that can be erased independently so it is possible to preserve valid data while old data is erased. program and erase commands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified. the command set required to control the memory is consistent with jedec standards. chip enable, output enable and write enable signals control the bus operation of the memory. they allow simple connection to most microprocessors, often without additional logic. the m29w256gh and m29w256gl support asynchronous random read and page read from all blocks of the memory array. the devices also feature a write to buffer program capability that improves the programming throughput by programming in one shot a buffer of 32 words/64 bytes. the enhanced buffered program feature is also available to speed up the programming throughput, allowing to program 256 words in one shot (only in x16 mode). the v pp /wp signal can be used to enable faster programming of the device. the m29w256gh and m29w256gl have an extra block, the extended block, of 128 words in x16 mode or of 256 bytes in x8 mode that can be accessed using a dedicated command. the extended block can be protected and so is useful for storing security information. however the protection is not reversible, once protected the protection cannot be undone. the device features different levels of hardware and software block protection to avoid unwanted program or erase (modify): ? hardware protection: ?the v pp /wp provides a hardware protection of the highest and lowest block on the m29w256gh, m29w256gl, respectively. ? software protection: ? volatile protection ? non-volatile protection ? password protection the m29w256gh and m29w256gl are offered in tsop56 (14 x 20 mm), and tbga64 (10 x 13 mm, 1 mm pitch), packages. the memories are delivered with all the bits erased (set to ?1?).
description m29w256gh, m29w256gl 8/98 figure 1. logic diagram 1. also see appendix a and table 37 for a full listing of the block addresses. table 2. signal names name description direction a0-a23 address inputs inputs dq0-dq7 data inputs/outputs i/o dq8-dq14 data inputs/outputs i/o dq15a ? 1 data input/output or address input i/o e chip enable input g output enable input w write enable input rp reset input rb ready/busy output output byte byte/word organization select input v ccq input/output buffer supply voltage supply v cc supply voltage supply v pp /wp (1) 1. v pp /wp may be left floating as it is internally connect ed to a pull-up resistor which enables program/erase operations. v pp /write protect supply/input v ss ground ? nc not connected ? ai13330b a0-a23 w dq0-dq14 v cc m29w256gh m29w256gl e v ss 15 g rp dq15a-1 rb v pp /wp byte v ccq 24
m29w256gh, m29w256gl description 9/98 figure 2. tsop connections dq3 dq9 dq2 a6 dq0 w a3 rb dq6 a19 a8 dq13 a17 a12 dq14 a2 dq12 dq10 dq15a-1 v cc dq4 dq5 a7 dq7 v pp /wp a21 ai13331b m29w256gh m29w256gl 14 1 15 28 29 42 43 56 dq8 nc a20 a1 a18 a4 a5 dq1 dq11 g a14 a15 a16 a13 byte a23 a22 v ss e a0 rp v ss a9 a10 a11 nc nc nc nc v ccq
description m29w256gh, m29w256gl 10/98 figure 3. tbga and lbga connections (top view through package) 6 5 4 3 2 1 v ss a11 a10 a8 a9 dq3 dq11 dq10 a18 v pp / wp rb a0 a2 a4 a3 g nc nc nc dq2 dq1 dq9 dq8 a6 a17 a7 dq4 v cc dq12 dq5 a19 a21 rp w a5 dq0 nc nc v ss a1 a20 dq7 byte c b a e d f g h dq15 a-1 8 7 ai11527 c nc a15 a14 a12 a13 dq6 dq13 dq14 a23 a22 nc v ss a16 nc nc e nc nc v ccq v ccq
m29w256gh, m29w256gl description 11/98 figure 4. block addresses ai13332 (x8) address lines a23-a0, dq15a-1 128 kbytes 1ffffffh 128 kbytes 00ffffh 000000h 128 kbytes 010000h total of 256 uniform blocks 01ffffh (x16) ad d ress l i n es a23-a0 64 kwords fffffh 64 kwords 007fffh 000000h 64 kwords
signal descriptions m29w256gh, m29w256gl 12/98 2 signal descriptions see figure 1: logic diagram , and table 2: signal names , for a brief overview of the signals connected to this device. 2.1 address inputs (a0-a23) the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the program/erase controller. 2.2 data inputs/outputs (dq0-dq7) the data i/o outputs the data stored at the selected address during a bus read operation. during bus write operations they represent the commands sent to the command interface of the internal state machine. 2.3 data inputs/outputs (dq8-dq14) the data i/o outputs the data stored at the selected address during a bus read operation when byte is high, v ih . when byte is low, v il , these pins are not used and are high impedance. during bus write operations the command register does not use these bits. when reading the status register these bits should be ignored. 2.4 data inputs/outputs or address inputs (dq15a ? 1) when the device is in x 16 bus mode, this pin behaves as a data input/output pin (as dq8- dq14). when the device operates in x 8 bus mode, this pin behaves as the least significant bit of the address. throughout the text consider references to the data input/output to include this pin when the device operates in x 16 bus mode and references to the address inputs to include this pin when the device operates in x 8 bus mode except when stated explicitly otherwise. 2.5 chip enable (e ) the chip enable pin, e , activates the memory, allowing bus read and bus write operations to be performed. when chip enable is high, v ih , all other pins are ignored. 2.6 output enable (g ) the output enable pin, g , controls the bus read operation of the memory.
m29w256gh, m29w256gl signal descriptions 13/98 2.7 write enable (w ) the write enable pin, w , controls the bus write operation of the memory?s command interface. 2.8 v pp /write protect (v pp /wp ) the v pp /write protect pin provides two functions. the v pph function allows the memory to use an external high voltage power supply to reduce the time required for program operations. this is achieved by bypassing the unlock cycles. the write protect function provides a hardware method of protecting the highest or lowest block (see section 1: description ). when v pp /write protect is low, v il , the highest or lowest block is protected. program and erase operations on this block are ignored while v pp /write protect is low. when v pp /write protect is high, v ih , the memory reverts to the previous protection status of the highest or lowest block. program and erase operations can now modify the data in this block unless the block is protected using block protection. when v pp /write protect is raised to v pph the memory automatically enters the unlock bypass mode (see section 6.2 ). when v pp /write protect is raised to v pph , the execution time of the command is lower (see table 21: program, erase times and program, erase endurance cycles ). when v pp /write protect returns to v ih or v il normal operation resumes. during unlock bypass program operations the memory draws i pp from the pin to supply the programming circuits. see the description of the unlock bypass command in the command interface section. the transitions from v ih to v pph and from v pph to v ih must be slower than t vhvpp (see figure 23: accelerated program timing waveforms ). never raise v pp /write protect to v pph from any mode except read mode, otherwise the memory may be left in an indeterminate state. a 0.1 f capacitor should be connected between the v pp /write protect pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during unlock bypass program (see i pp1 , i pp2 , i pp3 , i pp4 in table 27: dc characteristics ). the v pp /write protect pin may be left floating or unconnected because it features an internal pull-up. refer to table 3 for a summary of v pp /wp functions. table 3. v pp /wp functions v pp /wp function v il highest block protected on m29w256gh. lowest block protected on m29w256gl. v ih highest and lowest block unprotected unless a software protection is activated (see section 4: hardware protection ). v pph unlock bypass mode. it supplies the current needed to speed up programming.
signal descriptions m29w256gh, m29w256gl 14/98 2.9 reset (rp ) the reset pin can be used to apply a hardware reset to the memory. a hardware reset is achieved by holding reset low, v il , for at least t plpx . after reset goes high, v ih , the memory will be ready for bus read and bus write operations after t phel or t rhel , whichever occurs last. see section 2.10: ready/busy output (rb) , table 31: reset ac characteristics , figure 21 and figure 22 for more details. 2.10 ready/busy output (rb ) the ready/busy pin is an open-drain output that can be used to identify when the device is performing a program or erase operation. during program or erase operations ready/busy is low, v ol (see table 22: status register bits ). ready/busy is high-impedance during read mode, auto select mode and erase suspend mode. after a hardware reset, bus read and bus write operations cannot begin until ready/busy becomes high-impedance. see table 31: reset ac characteristics , figure 21 and figure 22 . the use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. 2.11 byte/word organization select (byte ) it is used to switch between the x8 and x16 bus modes of the memory. when byte/word organization select is low, v il , the memory is in x8 mode, when it is high, v ih , the memory is in x16 mode. 2.12 v cc supply voltage v cc provides the power supply for all operations (read, program and erase). the command interface is disabled when the v cc supply voltage is less than the lockout voltage, v lko . this prevents bus write operations from accidentally damaging the data during power-up, power-down and power surges. if the program/erase controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. a 0.1 f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations (see i cc1 , i cc2 , i cc3 in table 27: dc characteristics ). 2.13 v ccq input/output supply voltage v ccq provides the power supply to the i/o pins and enables all outputs to be powered independently from v cc .
m29w256gh, m29w256gl signal descriptions 15/98 2.14 v ss ground v ss is the reference for all voltage measurements. the device features two v ss pins both of which must be connected to the system ground.
bus operations m29w256gh, m29w256gl 16/98 3 bus operations there are five standard bus operations that control the device. these are bus read (random and page modes), bus write, output disable, standby and automatic standby. see table 4: bus operations, 8-bit mode and table 5: bus operations, 16-bit mode for a summary. typical glitches of less than 5 ns on chip enable, write enable, and reset pins are ignored by the memory and do not affect bus operations. 3.1 bus read bus read operations read from the memory cells, or specific registers in the command interface. to speed up the read operation the memory array can be read in page mode where data is internally read and stored in a page buffer. the page has a size of 8 words (or 16 bytes) and each word in the page is addressed by the address inputs a2-a0 in x 16 mode and a2-a0 plus dq15a ? 1 in byte mode. a valid bus read operation involves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable high, v ih . the data inputs/outputs will output the value, see figure 13: random read ac waveforms (8-bit mode) , figure 15: page read ac waveforms (16-bit mode) , and table 28: read ac characteristics , for details of when the output becomes valid. 3.2 bus write bus write operations write to the command interface. a valid bus write operation begins by setting the desired address on the address inputs. the address inputs are latched by the command interface on the falling edge of chip enable or write enable, whichever occurs last. the data inputs/outputs are latched by the command interface on the rising edge of chip enable or write enable, whichever occurs first. output enable must remain high, v ih , during the whole bus write operation. see figure 16 , and figure 17 , write ac waveforms, and table 29 and table 30 , write ac characteristics, for details of the timing requirements. 3.3 output disable the data inputs/outputs are in the high impedance state when output enable is high, v ih . 3.4 standby driving chip enable high in read mode, causes the memory to enter standby mode and the data inputs/outputs pins are placed in the high-impedance state. to reduce the supply current to the standby supply current, i cc2 , chip enable should be held within v cc 0.3v. for the standby current level see table 27: dc characteristics . during program or erase operations the memory will continue to use the program/erase supply current, i cc3 , for program or erase operations until the operation completes.
m29w256gh, m29w256gl bus operations 17/98 3.5 reset during reset mode the memory is deselected and the outputs are high impedance. the memory is in reset mode when rp is at v il . the power consumption is reduced to the standby level, independently from the chip enable, output enable or write enable inputs. 3.6 automatic standby automatic standby allows the memory to achieve low power consumption during read mode. after a read operation, if cmos levels (v cc 0.3 v) are used to drive the bus and the bus is inactive for t avqv +30ns or more, the memory enters automatic standby where the internal supply current is reduced to the standby supply current, i cc2 (see table 27: dc characteristics ). the data inputs/outputs will still output data if a bus read operation is in progress. the power supplier of data bus, v ccq , can have a null consumption (depending on load circuits connected with data bus) when the memory enters automatic standby. 3.7 auto select mode the auto select mode allows the system or the programming equipment to read the electronic signature, verify the protection status of the extended memory block, and apply/remove block protection. for example, this mode can be used by a programming equipment to automatically match a device and the application code to be programmed. there are two methods to enter auto select mode: ? programmer method: additional bus operations are used. they require v id to be applied to address pin a9. refer to table 6 , table 7 , tab l e 8 , and ta bl e 9 for a description of the bus operations required to read the electronic signature using the programmer method ? in-system method: the auto select mode is entered by issuing the auto select command (see section 6.1.2 ). it is not necessary to apply v id to a9. at power-up, the device is in read mode, and can then be put in auto select mode by using one of the methods described above. the device cannot enter auto select mode when a program or erase operation is ongoing (rb low). however, auto select mode can be entered if the erase operation has been suspended by issuing an erase suspend command (see section 6.1.6 ). the auto select mode is exited by performing a reset. the device is returned to read mode, except if the auto select mode was entered after an erase suspend or a program suspend command. in this case, it returns to the erase or program suspend mode.
bus operations m29w256gh, m29w256gl 18/98 3.7.1 read electronic signature the memory has two codes, the manufacturer code and the device code used to identify the memory. these codes can be accessed by performing read operations with control signals and addresses set as shown in table 6: read electronic signature - auto select mode - programmer method (8-bit mode) and table 7: read electronic signature - auto select mode - programmer method (16-bit mode) . these codes can also be accessed by issuing an auto select command (see section 6.1.2: auto select command ). 3.7.2 verify extended memory block protection indicator the extended memory block is either factory locked or customer lockable. the protection status of the extended memory block (factory locked or customer lockable) can be accessed by reading the extended memory block protection indicator. it can be read in auto select mode using either the programmer (see table 8 and ta bl e 9 ) or the in-system method (see ta bl e 1 2 and ta bl e 1 3 ). the protection status of the extended memory block is then output on bit dq7 of the data input/outputs (see table 4 and table 5 , bus operations in 8-bit and 16-bit mode). 3.7.3 verify block protection status the protection status of a block can be directly accessed by performing a read operation with control signals and addresses set as shown in tab l e 8 and table 9 . if the block is protected, then 0001h (in x 16 mode) is output on data input/outputs dq0- dq15, otherwise 0000h is output. 3.7.4 hardware block protect the v pp /wp pin can be used to protect the highest or lowest block. when v pp /wp is at v il the highest (m29w256gh) or lowest block (m29w256gl) is protected and remains protected regardless of the block protection status or the reset pin state.
m29w256gh, m29w256gl bus operations 19/98 m table 4. bus operations, 8-bit mode operation (1) e g w rp v pp /wp address inputs data inputs/outputs a23, a0, dq15a-1 dq14-dq8 dq7-dq0 bus read v il v il v ih v ih x cell address hi-z data output bus write v il v ih v il v ih x (2) command address hi-z data input (3) standby v ih xxv ih x x hi-z hi-z output disable v il v ih v ih v ih x x hi-z hi-z reset x x x v il x x hi-z hi-z 1. x = v il or v ih . 2. if wp is low, v il , the outermost block remains protected. 3. data input as required when issuing a command sequence, performing data polling or block protection. table 5. bus operations, 16-bit mode operation (1) e g w rp v pp /wp address inputs data inputs/outputs a23, a0 dq15a-1, dq14-dq0 bus read v il v il v ih v ih x cell address data output bus write v il v ih v il v ih x (2) command address data input (3) standby v ih xxv ih x x hi-z output disable v il v ih v ih v ih x x hi-z reset xxxv il x x hi-z 1. x = v il or v ih . 2. if wp is low, v il , the outermost block remains protected. 3. data input as required when issuing a command sequence, performing data polling or block protection.
bus operations m29w256gh, m29w256gl 20/98 table 6. read electronic signature - auto select mode - programmer method (8-bit mode) read cycle (1) e g w address inputs data inputs/outputs a23-a10 a9 a8-a7 a6 a5-a4 a3 a2 a1 a0 dq15a-1 dq14-dq8 dq7-dq0 manufacturer code v il v il v ih x v id (2) xv il x v il v il v il v il xx 20h device code (cycle 1) v il v il v il v ih xx 7eh (both devices) device code (cycle 2) v ih v ih v ih v il xx 22h (both devices) device code (cycle 3) v ih v ih v ih v ih xx 01h (both devices) 1. x = v il or v ih . 2. when using the in-system method, applying v id to a9 is not required. a9 can be either v il or v ih . table 7. read electronic signature - auto select mode - programmer method (16-bit mode) read cycle (1) e g w address inputs data inputs/outputs a23-a10 a9 a8-a7 a6 a5-a4 a3 a2 a1 a0 dq15a-1, dq14-dq0 manufacturer code v il v il v ih x v id (2) xv il x v il v il v il v il 0020h device code (cycle 1) v il v il v il v ih 227eh (both devices) device code (cycle 2) v ih v ih v ih v il 2222h (both devices) device code (cycle 3) v ih v ih v ih v ih 2201h (both devices) 1. x = v il or v ih . 2. when using the in-system method, applying v id to a9 is not required. a9 can be either v il or v ih .
m29w256gh, m29w256gl bus operations 21/98 table 8. block protection - auto select mode - programmer method (8-bit mode) operation (1) e g w address inputs data inputs/outputs a23- a16 a14- a10 a9 a8- a7 a6 a5- a4 a3- a2 a1 a0 dq15 a-1 dq14 -dq8 dq7-dq0 verify extended memory block protection indicator (bit dq7) m29w256gl v il v il v ih x x v id (2) xv il xv il v ih v ih xx 89h (factory locked) 09h (customer lockable) m29w256gh 99h (factory locked) 19h (customer lockable) verify block protection status bad v il 01h (protected) 00h (unprotected) 1. x = v il or v ih . bad any address in the block. 2. when using the in-system method, applying v id to a9 is not required. a9 can be either v il or v ih . table 9. block protection - auto select mode - programmer method (16-bit mode) operation (1) e g w address inputs data inputs/outputs a23- a16 a14- a10 a9 a8- a7 a6 a5- a4 a3- a2 a1 a0 dq15a-1, dq14-dq0 verify extended memory block indicator (bit dq7) m29w256gl v il v il v ih x x v id (2) xv il xv il v ih v ih 0089h (factory locked) 0009h (customer lockable) m29w256gh 0099h (factory locked) 0019h (customer lockable) verify block protection status bad v il 0001h (protected) 0000h (unprotected) 1. x = v il or v ih . bad any address in the block. 2. when using the in-system method, applying v id to a9 is not required. a9 can be either v il or v ih .
hardware protection m29w256gh, m29w256gl 22/98 4 hardware protection the m29w256gh and m29w256gl feature a v pp /wp pin that protects the highest or lowest block. refer to section 2: signal descriptions for a detailed description of the signal. 5 software protection the m29w256gh and m29w256gl have three different software protection modes: ? volatile protection ? non-volatile protection ? password protection on first use all parts default to operate in non-volatile protection mode and the customer is free to activate the non-volatile or the password protection mode. the desired protection mode is activated by setting either the one-time programmable non- volatile protection mode lock bit, or the password protection mode lock bit of the lock register (see section 5.4: lock register ). programming the non-volatile protection mode lock bit or the password protection mode lock bit, to ?0? will permanently activate the non-volatile or the password protection mode, respectively. these two bits are one-time programmable and non-volatile: once the protection mode has been programmed, it cannot be changed and the device will permanently operate in the selected protection mode. it is recommended to activate the desired software protection mode when first programming the device. the non-volatile and password protection modes both provide non-volatile protection. volatilely protected blocks and non-volatilely protected blocks can co-exist within the memory array. however, the volatile protection only control the protection scheme for blocks that are not protected using the non-volatile or password protection. if the user attempts to program or erase a protected block, the device ignores the command and returns to read mode. the device is shipped with all blocks unprotected. the block protection status can be read either by performing a read electronic signature (see table 6 and ta bl e 7 ) or by issuing an auto select command (see table 11: block protection status ). for the lowest and highest blocks, an even higher level of block protection can be achieved by locking the blocks using the non-volatile protection and then by holding the v pp /wp pin low.
m29w256gh, m29w256gl software protection 23/98 5.1 volatile protection mode the volatile protection allows the software application to easily protect blocks against inadvertent change. however, the protection can be easily disabled when changes are needed. volatile protection bits, vpbs, are volatile and unique for each block and can be individually modified. vpbs only control the protection scheme for unprotected blocks that have their non-volatile protection bits, nvpbs, cleared (erased to ?1?) (see section 5.2: non- volatile protection mode and section 6.4.4: non-volatile protection mode command set ). by issuing the vpb program or vpb clear commands, the vpbs are set (programmed to ?0?) or cleared (erased to ?1?), thus placing each block in the protected or unprotected state respectively. the vpbs can be set (programmed to ?0?) or cleared (erased to ?1?) as often as needed. when the parts are first shipped, or after a power-up or hardware reset, the vpbs can be set or cleared depending upon the ordering option chosen: ? if the option to clear the vpbs after power-up is selected, then the blocks can be programmed or erased depending on the nvpbs state (see table 11: block protection status ) ? if the option to set the vpbs after power-up is selected, the blocks default to be protected. refer to section 6.4.3 for a description of the volatile protection mode command set. 5.2 non-volatile protection mode 5.2.1 non-volatile protection bits a non-volatile protection bit (nvpb) is assigned to each block. when a nvpb is set to ?0?, the associated block is protected, preventing any program or erase operations in this block. the nvpb bits are set individually by issuing a nvpb program command. they are non- volatile and will remain set through a hardware reset or a power-down/power-up sequence. the nvpbs cannot be cleared individually, they can only be cleared all at the same time by issuing a clear all non-volatile protection bits command. the nvpbs can be protected all at a time by setting a volatile bit, the nvpb lock bit (see section 5.2.2: non-volatile protection bit lock bit ). if one of the non-volatile protected blocks needs to be unprotected (corresponding nvpb set to ?1?), a few more steps are required: 1. first, the nvpb lock bit must be cleared by either putting the device through a power cycle, or hardware reset 2. the nvpbs can then be changed to reflect the desired settings 3. the nvpb lock bit must be set once again to lock the nvpbs. the device operates normally again. note: 1 to achieve the best protection, it is recommended to execute the nvpb lock bit program command early in the boot code and to protect the boot code by holding v pp /wp low, v il . 2 the nvpbs and vpbs have the same function when v pp /wp pin is high, v ih , as they do when v pp /wp pin is at the voltage for program acceleration (v pph ).
software protection m29w256gh, m29w256gl 24/98 refer to table 11: block protection status and figure 5: software protection scheme for details on the block protection mechanism, and to section 6.4.4 for a description of the non- volatile protection mode command set. 5.2.2 non-volatile protection bit lock bit the non-volatile protection bit lock bit (nvpb lock bit) is a global volatile bit for all blocks. when set (programmed to ?0?), it prevents changing the state of the nvpbs. when cleared (programmed to ?1?), the nvpbs can be set and reset using the nvpb program command and clear all nvpbs command, respectively. there is only one nvpb lock bit per device. refer to section 6.4.5 for a description of the nvpb lock bit command set. note: 1 no software command unlocks this bit unless the device is in password protection mode; it can be cleared only by taking the device through a hardware reset or a power-up. 2 the nvpb lock bit must be set (programmed to ?0?) only after all nvpbs are configured to the desired settings. 5.3 password protection mode the password protection mode provides an even higher level of security than the non- volatile protection mode by requiring a 64-bit password for unlocking the device nvpb lock bit. in addition to this password requirement, the nvpb lock bit is set ?0? after power-up and reset to maintain the device in password protection mode. successful execution of the password unlock command by entering the correct password clears the nvpb lock bit, allowing for block nvpbs to be modified. if the password provided is not correct, the nvpl lock bit remains locked and the state of the nvpbs cannot be modified. to place the device in password protection mode, the following steps are required: 1. prior to entering the password protection mode, it is necessary to set a 64-bit password and to verify it (see password protection mode command set on page 47 ). password verification is only allowed during the password programming operation 2. the password protection mode is then activated by programming the password protection mode lock bit to ?0?. this operation is not reversible and once the bit is programmed it cannot be erased, the device permanently remains in password protection mode, and the 64-bit password can neither be retrieved nor reprogrammed. moreover, all commands to the address where the password is stored, are disabled. refer to table 11: block protection status and figure 5: software protection scheme for details on the block protection scheme. refer to section 6.4.6 for a description of the password protection mode command set. note: there is no means to verify the password after it is set. if the password is lost after setting the password mode lock bit, there is no way to clear the nvpb lock bit.
m29w256gh, m29w256gl software protection 25/98 figure 5. software protection scheme 1. nvpbs default to ?1? (block unprotected) after power-up and hardware reset. a block is protected or unprotected when its nvpb is set to ?0? and ?1?, respectively. nvpbs are programmed individually and cleared collectively. 2. vpb default status depends on ordering option. a block is protected or unprotected when its vpb is set to ?0? and ?1?, respectively. vpbs are programmed and cleared individually. for the volatile protection to be effective, the nvpb lock bit must be set to ?0? (nvpb bits unlocked) and the block nvpb must be set to ?1? (block unprotected). 3. the nvpb lock bit is volatile and default to ?1? (nvpb bits unlocked) after power-up and hardware reset. nvpb bits are locked by setting the nvpb lock bit to ?0?. once programmed to ?0 ?, the nvpb lock bit can be reset to ?1? only be taking the device through a power-up or hardware reset. 5.4 lock register the lock register is a 16-bit one-time programmable register. the bits in the lock register are summarized in table 10: lock register bits . the lock register allows configuration of memory blocks and extended memory block protection (see table 11: block protection status ). see section 6.4.1: lock register command set for a description of the commands allowing to read and program the lock register. 5.4.1 extended block protection bit (dq0) if the device has not been shipped with the extended memory block factory locked, the block can be protected by setting the extended memory block protection bit, dq0, to ?0?. however, this bit is one-time programmable and once protected the extended memory block cannot be unprotected. the extended memory block protection status can be read in auto select mode either by applying v id to a9 (see ta bl e 8 and table 9 ) or by issuing an auto select command (see table 12 and table 13 ). ai13676 parameter block or main block nvpb (1) vpb (2) non-volatile protection mode volatile protection non-volatile protection password protection mode nvpb lock bit (3)
software protection m29w256gh, m29w256gl 26/98 5.4.2 non-volatile protection mode lock bit (dq1) the non-volatile protection mode lock bit, dq1, is one-time programmable. programming (change the first apex to ?0?) this bit permanently places the device in non-volatile protection mode. by default the memory operates in non-volatile protection mode independently whether the non-volatile protection mode lock bit, dq1, is programmed. from factory the memory blocks can be either unprotected (change the first apex to ?1?) or protected (change the first apex to ?0?), according to the ordering option that has been chosen. any attempt to program the non-volatile protection mode lock bit when the password protection mode bit is programmed causes the operation to abort and the device to return to read mode. 5.4.3 password protection mode lock bit (dq2) the password protection mode lock bit, dq2, is one-time programmable. programming (setting to ?0?) this bit permanently places the device in password protection mode. any attempt to program the password protection mode lock bit when the non-volatile protection mode bit is programmed causes the operation to abort and the device to return to read mode. 5.4.4 dq15 to dq3 reserved dq15 to dq3 are reserved and during programming they must be held at '1'. table 10. lock register bits (1) 1. dq0, dq1 and dq2 lock register bits are set to ?1? when shipped from the factory. dq15-3 dq2 dq1 dq0 reserved password protection mode lock bit non-volatile protection mode lock bit extended block protection bit table 11. block protection status nvpb lock bit (1) 1. if the nvpb lock bit is set to ?0?, all nvpbs are lock ed. if the nvpb lock bit is set to ?1?, all nvpbs are unlocked. block nvpb (2) block vpb (3) block protection status block protection status 0 0 x 01h block protected (non-volatile protection through nvpb) 0 1 1 00h block unprotected 01000h block protected (volatile protection through vpb) 10x01h block protected (non-volatile protection through nvpb) 11001h block protected (volatile protection through vpb) 1 1 1 00h block unprotected
m29w256gh, m29w256gl software protection 27/98 figure 6. lock register program flowchart 1. pd is the programmed data (see table 10: lock register bits ). 2. the lock register can only be programmed once. 2. if the block nvpb is set to ?0?, the block is protected, if set to ?1?, it is unprotected. 3. if the block vpb is set to ?0?, the block is protected, if set to ?1?, it is unprotected. start pass: write lock register exit command: add dont' care, data 90h add dont' care, data 00h ai13677 done yes yes no dq5 = 1 no write unlock cycles: add 555h, data aah add 2aah, data 55h unlock cycle 1 unlock cycle 2 write enter lock register command set: add 555h, data 40h program lock register data: add dont' care, data a0h add dont' care (1) , data pdh polling algorithm device returned to read mode fail reset to return the device to read mode
command interface m29w256gh, m29w256gl 28/98 6 command interface all bus write operations to the memory are interpreted by the command interface. commands consist of one or more sequential bus write operations. failure to observe a valid sequence of bus write operations will result in the memory returning to read mode. the long command sequences are imposed to maximize data security. the address used for the commands changes depending on whether the memory is in 16- bit or 8-bit mode. 6.1 standard commands see either ta bl e 12 , or ta bl e 1 3 , depending on the configuration that is being used, for a summary of the standard commands. 6.1.1 read/reset command the device is in read mode after reset or after power-up. the read/reset command returns the memory to read mode. it also resets the errors in the status register. either one or three bus write operations can be used to issue the read/reset command. the read/reset command can be issued, between bus write cycles before the start of a program or erase operation, to return the device to read mode. if the read/reset command is issued during the timeout of a block erase operation, the memory will take up to 10 s to abort. during the abort period no valid data can be read from the memory. the read/reset command will not abort an erase operation when issued while in erase suspend. 6.1.2 auto select command the auto select command puts the device in auto select mode, when using the in-system method (see section 3.7: auto select mode ). when in auto select mode, the system can read the manufacturer code, the device code, the protection status of each block (block protection status) and the extended memory block protection indicator. three consecutive bus write operations are required to issue the auto select command. once the auto select command is issued bus read operations to specific addresses output the manufacturer code, the device code, the extended memory block protection indicator and a block protection status (see table 12 and table 13 in conjunction with table 6 , table 7 , table 8 , and table 9 ). the memory remains in auto select mode until a read/reset or cfi query command is issued.
m29w256gh, m29w256gl command interface 29/98 6.1.3 read cfi query command the memory contains an information area, named cfi data structure, which contains a description of various electrical and timing parameters, density information and functions supported by the memory. see appendix b , ta bl e 39 , table 40 , table 41, table 42, table 43 and ta bl e 44 for details on the information contained in the common flash interface (cfi) memory area. the read cfi query command is used to put the memory in read cfi query mode. once in read cfi query mode, bus read operations to the memory will output data from the common flash interface (cfi) memory area. one bus write cycle is required to issue the read cfi query command. this command is valid only when the device is in the read array or auto select mode. the read/reset command must be issued to return the device to the previous mode (the read array mode or auto select mode). a second read/reset command is required to put the device in read array mode from auto select mode. 6.1.4 chip erase command the chip erase command can be used to erase the entire chip. six bus write operations are required to issue the chip erase command and start the program/erase controller. if some block are protected, then these are ignored and all the other blocks are erased. if all of the blocks are protected the chip erase operation appears to start but will terminate within about 100 s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the erase operation the memory will ignore all commands, including the erase suspend command. it is not possible to issue any command to abort the operation. typical chip erase times are given in table 21 . all bus read operations during the chip erase operation will output the status register on the data inputs/outputs. see section 7: status register for more details. after the chip erase operation has complete d the memory will retu rn to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. the chip erase command sets all of the bits in unprotected blocks of the memory to ?1?. all previous data is lost. the chip erase operation is aborted by performing a reset or powering down the device. in this case, data integrity cannot be ensured, and it is recommended to erase again the entire chip. 6.1.5 block erase command the block erase command can be used to erase a list of one or more blocks. it sets all of the bits in the unprotected selected blocks to ?1?. all previous data in the selected blocks is lost.
command interface m29w256gh, m29w256gl 30/98 six bus write operations are required to select the first block in the list. each additional block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. after the command sequence is written, a block erase timeout occurs. during the timeout period, additional sector addresses and sector erase commands may be written. once the program/erase controller has started, it is not possible to select any more blocks. each additional block must therefore be selected within the timeout period of the last block. the timeout timer restarts when an additional block is selected. after the sixth bus write operation, a bus read operation outputs the status register. see figure 16: write enable controlled program waveforms (8-bit mode) and figure 17: write enable controlled program waveforms (16-bit mode) for details on how to identify if the program/erase controller has started the block erase operation. after the block erase operation has completed, the memory returns to the read mode, unless an error has occurred. when an error occurs, bus read operati ons will continue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. if any selected blocks are protected then these are ignored and all the other selected blocks are erased. if all of the selected blocks are protected the block erase operation appears to start but will terminate within about 100 s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the block erase operation the memory ignores all commands except the erase suspend command and the read/reset command which is only accepted during the timeout period. typical block erase time and block erase timeout are given in ta bl e 2 1 . the block erase operation is aborted by performing a reset or powering down the device. in this case, data integrity cannot be ensured, and it is recommended to erase again the blocks aborted. 6.1.6 erase suspend command the erase suspend command can be used to temporarily suspend a block erase operation. one bus write operation is required to issue the command together with the block address. the program/erase controller suspends the erase operation within the erase suspend latency time of the erase suspend command being issued. however, when the erase suspend command is written during the block erase timeout, the device immediately terminates the timeout period and suspends the erase operation. once the program/erase controller has stopped, the memory operates in read mode and the erase is suspended. during erase suspend it is possible to read and execute program or write to buffer program operations in blocks that are not suspended; both read and program operations behave as normal on these blocks. reading from blocks that are suspended will output the status register. if any attempt is made to program in a protected block or in the suspended block then the program command is ignored and the data remains unchanged. in this case the status register is not read and no error condition is given. it is also possible to issue the auto select (after entering autoselect mode), read cfi query and unlock bypass commands during an erase suspend. the read/reset command must be issued to return the device to read array mode before the resume command will be accepted.
m29w256gh, m29w256gl command interface 31/98 during erase suspend a bus read operation to the extended memory block will output the extended memory block data. once in the extended block mode, the exit extended block command must be issued before the erase operation can be resumed. the erase suspend command is ignored if written during chip erase operations. refer to table 21: program, erase times and program, erase endurance cycles for the values of block erase timeout and block erase suspend latency time. if the erase suspend operation is aborted by performing a reset or powering down the device, data integrity cannot be ensured, and it is recommended to erase again the blocks suspended. 6.1.7 erase resume command the erase resume command is used to restart the program/erase controller after an erase suspend. the device must be in read array mode before the resume command will be accepted. an erase can be suspended and resumed more than once. 6.1.8 program command the program command can be used to program a value to one address in the memory array at a time. the command requires four bus write operations, the final write operation latches the address and data in the internal state machine and starts the program/erase controller. programming can be suspended and then resumed by issuing a program suspend command and a program resume command, respectively (see section 6.1.9: program suspend command and section 6.1.10: program resume command ). if the address falls in a protected block then the program command is ignored, the data remains unchanged. the status register is never read and no error condition is given. after programming has started, bus read operations output the status register content. see figure 16: write enable controlled program waveforms (8-bit mode) and figure 17: write enable controlled program waveforms (16-bit mode) for more details. typical program times are given in table 21: program, erase times and program, erase endurance cycles . after the program operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs, bus read operations to the memory continue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. one of the erase commands must be used to set all the bits in a block or in the whole memory from ?0? to ?1?. the program operation is aborted by performing a reset or powering-down the device. in this case data integrity cannot be ensured, and it is recommended to reprogram the word or byte aborted.
command interface m29w256gh, m29w256gl 32/98 6.1.9 program suspend command the program suspend command allows the system to interrupt a program operation so that data can be read from any block. when the program suspend command is issued during a program operation, the device suspends the program operation within the program suspend latency time (see table 21: program, erase times and program, erase endurance cycles ) and updates the status register bits. after the program operation has been suspended, the system can read array data from any address. however, data read from program-suspended addresses is not valid. the program suspend command may also be issued during a program operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the extended memory block area (one-time program area), the user must use the proper command sequences to enter and exit this region. the system may also issue the auto select command sequence when the device is in the program suspend mode. the system can read as many auto select codes as required. when the device exits the auto select mode, the device reverts to the program suspend mode, and is ready for another valid operation. see auto select command sequence for more information. if the program suspend operation is aborted by performing a reset or powering down the device, data integrity cannot be ensured, and it is recommended to program again the words or bytes aborted. 6.1.10 program resume command after the program resume command is issued, the device reverts to programming. the controller can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. refer to figure 16: write enable controlled program waveforms (8-bit mode) and figure 17: write enable controlled program waveforms (16-bit mode) for details. the system must issue a program resume command, to exit the program suspend mode and to continue the programming operation. further issuing of the resume command is ignored. another program suspend command can be written after the device has resumed programming.
m29w256gh, m29w256gl command interface 33/98 table 12. standard commands, 8-bit mode command (1) length bus operations (2) 1st 2nd 3rd 4th 5th 6th add data add data add data add data add data add data read/reset 1x f0 3 aaa aa 555 55 x f0 auto select manufacturer code 3 aaa aa 555 55 aaa 90 (3)(4) (3)(4) device code extended memory block protection indicator block protection status program (5) 4 aaa aa 555 55 aaa a0 pa pd chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 block erase 6+ aaa aa 555 55 aaa 80 aaa aa 555 55 bad 30 erase/program suspend 1 x b0 erase/program resume 1 x 30 read cfi query 1 aa 98 1. the device doesn?t tolerate ffh as a valid command, and on ce ffh is issued to the device, the m29dw127g will enter unexpected state. adding a f0h command systematically after ffh command is necessary. 2. x don?t care, pa program address, pd program data, bad any address in the block. all values in the table are in hexadecimal. 3. these cells represent read cycles. the other cells are write cycles. 4. the auto select addresses and data are given in table 6: read electronic signature - auto select mode - programmer method (8-bit mode) , and table 8: block protection - auto select mode - programmer method (8-bit mode) , except for a9 that is ?don?t care?. 5. in unlock bypass, the first two unlock cycles are no more needed (see table 16: write to buffer commands, 8-bit mode and table 17: write to buffer commands, 16-bit mode ).
command interface m29w256gh, m29w256gl 34/98 table 13. standard commands, 16-bit mode command (1) length bus operations (2) 1st 2nd 3rd 4th 5th 6th add data add data add data add data add data add data read/reset 1x f0 3 555 aa 2aa 55 x f0 auto select manufacturer code 3 555 aa 2aa 55 555 90 (3)(4) (3)(4) device code extended memory block protection indicator block protection status program (5) 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 block erase 6+ 555 aa 2aa 55 555 80 555 aa 2aa 55 bad 30 erase/program suspend 1 x b0 erase/program resume 1 x 30 read cfi query 1 55 98 1. the device doesn?t tolerate ffh as a valid command, and on ce ffh is issued to the device, the m29dw127g will enter unexpected state. adding a f0h command systematically after ffh command is necessary. 2. x don?t care, pa program address, pd program data, bad any address in the block. all values in the table are in hexadecimal. 3. these cells represent read cycles. the other cells are write cycles. 4. the auto select addresses and data are given in table 7: read electronic signature - auto select mode - programmer method (16-bit mode) , and table 9: block protection - auto select mode - programmer method (16-bit mode) , except for a9 that is ?don?t care?. 5. in unlock bypass, the first two unlock cycles are no more needed (see table 16 and table 17 ).
m29w256gh, m29w256gl command interface 35/98 6.2 unlock bypass command the unlock bypass command is used to place the device in unlock bypass mode. when the device enters the unlock bypass mode, the two initial unlock cycles required in the standard program command sequence are no more needed, and only two write cycles are required to program data, instead of the normal four cycles (see note 5. below ta bl e 1 2 and table 13 ). this results in a faster total programming time. unlock bypass command is consequently used in conjunction with the unlock bypass program command to program the memory faster than with the standard program commands. when the cycle time to the device is long, considerable time saving can be made by using these commands. three bus write operations are required to issue the unlock bypass command. when in unlock bypass mode, only the unlock bypass program, unlock bypass block erase, unlock bypass chip erase, and unlock bypass reset commands are valid: ? the unlock bypass program command can be issued to program addresses within the memory. ? the unlock bypass block erase command can then be issued to erase one or more memory blocks. ? the unlock bypass chip erase command can be issued to erase the whole memory array. ? the unlock bypass write to buffer program command can be issued to speed up programming operation. ? the unlock bypass reset command can be issued to return the memory to read mode. in unlock bypass mode the memory can be read as if in read mode. 6.2.1 unlock bypass program command the unlock bypass program command can be used to program one address in the memory array at a time. the command requires two bus write operations, the final write operation latches the address and data and starts the program/erase controller. the program operation using the unlock bypass program command behaves identically to the program operation using the program command. the operation cannot be aborted, a bus read operation to the memory outputs the status register (see section 6.1.8: program command for details on the behavior). 6.2.2 unlock bypass block erase command the unlock bypass block erase command can be used to erase one or more memory blocks at a time. the command requires two bus write operations instead of six using the standard block erase command. the final bus write operation latches the address of the block and starts the program/erase controller. to erase multiple block (after the first two bus write operations have selected the first block in the list), each additional block in the list can be selected by repeating the second bus write operation using the address of the additional block. the unlock bypass block erase command behaves in the same way as the block erase command: the operation cannot be aborted, and a bus read operation to the memory outputs the status register (see section 6.1.5: block erase command command for details).
command interface m29w256gh, m29w256gl 36/98 6.2.3 unlock bypass chip erase command the unlock bypass chip erase command can be used to erase all memory blocks at a time. the command requires two bus write operations only instead of six using the standard chip erase command. the final bus write operation starts the program/erase controller. the unlock bypass chip erase command behaves in the same way as the chip erase command: the operation cannot be aborted, and a bus read operation to the memory outputs the status register (see section 6.1.4: chip erase command command for details). 6.2.4 unlock bypass write to buffer program command the unlock bypass write to buffer command can be used to program the memory in fast program mode (see section 6.3.1: write to buffer program command set set for details). the command requires two bus write operations less than the standard write to buffer program command. the unlock bypass write to buffer program command behaves in the same way as the write to buffer program command: the operation cannot be aborted and a bus read operation to the memory outputs the status register. the write to buffer program confirm command is used to confirm an unlock bypass write to buffer program command and to program the n+1 words/bytes loaded in the write buffer by this command. 6.2.5 unlock bypass reset command the unlock bypass reset command can be used to return to read/reset mode from unlock bypass mode. two bus write operations are required to issue the unlock bypass reset command. read/reset command does not exit from unlock bypass mode. table 14. unlock bypass commands, 8-bit mode command length bus write operations (1) 1. x don?t care pa program address, pd program data, bad any address in the block, wbl write buffer location. all values in the table are in hexadecimal. 1st 2nd 3rd add data add data add data unlock bypass 3 aaa aa 555 55 aaa 20 unlock bypass program 2 x a0 pa pd unlock bypass block erase 2+ x 80 bad 30 unlock bypass chip erase 2 x 80 x 10 unlock bypass reset 2 x 90 x 0
m29w256gh, m29w256gl command interface 37/98 6.3 fast program commands the m29w256gh/l offers a set of fast program commands to improve the programming throughput: ? write to buffer program ? enhanced buffered program (valid in x 16 mode only) see either table 16 , table 17 or ta bl e 1 8 depending on the configuration that is being used, for a summary of the fast program commands. after programming has started, bus read operations in the memory output the status register content. write to buffer program command can be suspended and then resumed by issuing a program suspend command and a program resume command, respectively (see section 6.1.9: program suspend command and section 6.1.10: program resume command ). 6.3.1 write to buffer program command set the write to buffer program command set makes use of the device's 32-word/64-byte write buffer to speed up programming. 32 words/64 bytes can be loaded into the write buffer. each write buffer has the same a23-a5 addresses. the write to buffer program command dramatically reduces system programming time compared to the standard non-buffered program command. when issuing a write to buffer program command, the vpp/wp pin can be either held high, vih, or raised to vpph. see tab l e 16 , table 17 or table 18 for details on typical write to buffer program times in both cases. table 15. unlock bypass commands, 16-bit mode command length bus write operations (1) 1. x don't care, pa program address, pd program data, bad any address in the block, wbl write buffer location. all values in the table are in hexadecimal. 1st 2nd 3rd add data add data add data unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program 2 x a0 pa pd unlock bypass block erase 2+ x 80 bad 30 unlock bypass chip erase 2 x 80 x 10 unlock bypass reset 2 x 90 x 0
command interface m29w256gh, m29w256gl 38/98 write to buffer program command five successive steps are required to issue the write to buffer program command: 1. the write to buffer program command starts with two unlock cycles 2. the third bus write cycle sets up the write to buffer program command. the setup code can be addressed to any location within the targeted block. 3. the fourth bus write cycle sets up the number of words/bytes to be programmed. value n is written to the same block address, where n+1 is the number of words/bytes to be programmed. n+1 must not exceed the size of the write buffer or the operation will abort. 4. the fifth cycle loads the first address and data to be programmed. 5. use n bus write cycles to load the address and data for each word/byte into the write buffer. addresses must lie within the range from the start address+1 to the start address +n-1. optimum performance is obtained when the start address corresponds to a 32-word/ 64-byte boundary. if the start address is not aligned to a 32-word/64-byte boundary, the total programming time is doubled. all the addresses used in the write to buffer program operation must lie within the same page. to program the content of the write buffer, this command must be followed by a write to buffer program confirm command. if an address is written several times during a write to buffer program operation, the address/data counter will be decremented at each data load operation and the data will be programmed to the last word loaded into the buffer. invalid address combinations or failing to follow the correct sequence of bus write cycles will abort the write to buffer program. the status register bits dq1, dq5, dq6, dq7 can be used to monitor the device status during a write to buffer program operation. it is possible to detect program operation fails when changing programmed data from '0' to '1', that is when reprogramming data in a portion of memory already programmed. the resulting data will be the logical or between the previous value and the current value. after the write to buffer program operation has completed, the memory will return to read mode, unless an error has occurred. when an error occurring bus read operations to the memory will continue to output the status register.
m29w256gh, m29w256gl command interface 39/98 table 16. write to buffer commands, 8-bit mode command length bus write operations (1) 1. x don?t care, pa program address, pd program data, bad any address in the block, wbl write buffer location. all values in the table are in hexadecimal. 1st 2nd 3rd 4th 5th 6th add data add data add data add data add data add data write to buffer program n+5 aaa aa 555 55 bad 25 bad n (2) 2. the maximum number of cycles in the command sequence is 68. n+1 is the number of bytes to be programmed during the write to buffer program operation. pa (3) 3. each buffer has the same a23-a5 addresses. a0-a4 and a-1 are used to select a byte within the n+1 byte page. pd wbl (4) 4. the 6th cycle has to be issued n time. wbl scans the word inside the page. pd unlock bypass write to buffer program n+3 bad 25 bad n (2) pa (3) pd wbl (6) pd write to buffer program confirm 1 bad (5) 5. bad must be identical to the address loaded during the write to buffer program 3rd and 4th cycles. 6. the 4th cycle has to be issued n time. wbl scans the word inside the page. 29 buffered program abort reset 3 aaa aa 555 55 aaa f0 table 17. write to buffer commands, 16-bit mode command length bus write operations (1) 1. x don?t care, pa program address, pd program data, bad any address in the block, wbl write buffer location. all values in the table are in hexadecimal. 1st 2nd 3rd 4th 5th 6th add data add data add data add data add data add data write to buffer program n+5 555 aa 2aa 55 bad 25 bad n (2) 2. the maximum number of cycles in the command sequence is 36. n+1 is the number of words to be programmed during the write to buffer program operation. pa (3) 3. each buffer has the same a23-a5 addresses. a0-a4 are used to select a word within the n+1 word page. pd wbl (4) 4. the 6th cycle has to be issued n time. wbl scans the word inside the page. pd unlock bypass write to buffer program n+3 bad 25 bad n (2) pa (3) pd wbl (6) pd write to buffer program confirm 1 bad (5) 5. bad must be identical to the address loaded during the write to buffer program 3rd and 4th cycles. 6. the 4th cycle has to be issued n time. wbl scans the word inside the page. 29 buffered program abort reset 3 555 aa 2aa 55 555 f0
command interface m29w256gh, m29w256gl 40/98 buffered program abort reset command a buffered program abort reset command must be issued to reset the error condition and return to read mode. one of the erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. the write to buffer programming sequence can be aborted in the following ways: ? load a value that is greater than the page buffer size during the number of locations to program step in the write to buffer program command. ? write to an address in a block different than the one specified during the write-buffer load command. ? write an address/data pair to a different write-buffer-page than the one selected by the starting address during the write buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles. ? load address/data pairs in an incorrect sequence during the enhanced buffered program. the abort condition is indicated by dq1 = 1, dq6 = toggle, and dq5 = 0 (all of which are status register bits). a buffered program abort and reset command sequence must be written to reset the device for the next operation. note that the full 3-cycle buffered program abort and reset command sequence is required when using write to buffer and enhanced buffered programming features in unlock bypass mode. see appendix d , figure 29: write to buffer program flowchart and pseudocode , for a suggested flowchart on using the write to buffer program command. 6.3.2 enhanced buffered program command set the enhanced buffered program command set is available only in x 16 mode. enhanced buffered entry command enhanced buffered entry command is used in order to allow the execution of the enhanced buffered program. once issued the enhanced buffered entry command, it is possible to execute enhanced buffered program command more then one time; there is no need to repeat it again. after an enhanced buffered entry command only the commands belonging to the enhanced buffered program command set are accepted. enhanced buffered program command set is listed below: ? enhanced buffered program command ? enhanced buffered program abort reset ? enhanced buffered program exit after these commands any other command is ignored. in order to be sure that the entry procedure has successfully completed and the device is ready to receive one of the commands listed above it is recommended to monitor toggle bit (dq6), see figure 9: data toggle flowchart .
m29w256gh, m29w256gl command interface 41/98 enhanced buffered exit command the enhanced buffered exit command is used to return the device to read mode; before this command any other command, except the enhanced buffered program command set, is ignored. two bus write operations are required to issue the command. enhanced buffered program command the enhanced buffered program command, available only in x 16 mode, makes use of the device's 256-word write buffer to speed up programming. 256 words can be loaded into the write buffer. each write buffer has the same a23-a8 addresses. the enhanced buffered program command dramatically reduces system programming time compared to both the standard non-buffered program command and the write to buffer command. when issuing an enhanced buffered program command, the vpp/wp pin can be either held high, vih, or raised to vpph (see table 21: program, erase times and program, erase endurance cycles for details on typical enhanced buffered program times in both cases). ? enhanced buffered program command is accepted only after enhanced buffered entry command. ? only one bus write cycle is needed to set up the enhanced buffered program command. the setup code can be addressed to any location within the targeted block. ? the second bus write cycle loads the first address and data to be programmed. there a total of 256 address and data loading cycles. ? once the 256 words are loaded to the buffer a further bus write is needed to program the content of the write buffer. ? once enhanced buffered program is completed enhanced buffered exit command is required to return to read mode. (see table 18: enhanced buffered program commands, 16-bit mode for more details); note that address/data cycles must be loaded in an increasing address order (from add[7:0]=00000000 to add[7:0]=11111111) and completely (all 256 words). invalid address combinations or failing to follow the correct sequence of bus write cycles will abort the enhanced buffered program. the status register bits dq1, dq5, dq6, and dq7 can be used to monitor the device status during an enhanced buffered program operation. an external supply (12 v) can be used to improve programming efficiency. it is possible to detect program operation fails when changing programmed data from '0' to '1', that is when reprogramming data in a portion of memory already programmed. the resulting data will be the logical or between the previous and the current value. see appendix d and figure 30: enhanced buffered program flowchart and pseudocode , for a suggested flowchart on using the enhanced buffered program command. enhanced buffered program abort reset command after an enhanced buffered program abort the memory does not accept any other command; in order to reset the device from the abort must be issued an enhanced buffered program abort reset. after the enhanced buffered program abort reset command the memory waits for one of the enhanced buffered program command set.
command interface m29w256gh, m29w256gl 42/98 the enhanced buffered programming sequence can be aborted in the following ways: ? write to an address in a block different than the one specified during the buffer load. ? write an address/data pair to a different buffer-page than the one selected by the starting address during the buffer data loading stage of the operation ? write data other than the confirm command after the 256 data load cycles. ? load address/data pairs in an incorrect sequence during the enhanced buffered program. ? load a number of data that is less or greater than 256 during the program step. the abort condition is indicated by dq1 = 1, dq6 = toggle, and dq5 = 0 (all of which are status register bits). note: enhanced buffered program commands are available for x 16 mode only. table 18. enhanced buffered program commands, 16-bit mode command length bus write operations 1st 2nd 3rd ... 256th 257th 258th add data add data add data add data add data add data add data enter enhanced buffered program command set 3 555 aa 2aa 55 555 38 enhanced buffered program 258 bad 33 bad (00) data bad (01) data ... ... bad (fe) data bad (ff) data bad (00) 29 exit enhanced buffered program command set 2x90x00 enhanced buffered program abort reset 3 555 aa 2aa 55 555 f0
m29w256gh, m29w256gl command interface 43/98 6.4 protection commands blocks can be protected individually against accidental program, erase or read operations. the device block protection scheme is shown in figure 5: software protection scheme . see either table 19 , or table 20 , depending on the configuration that is being used, for a summary of the block protection commands. block protection commands are available both in 8-bit and 16-bit configuration. the memory block and extended memory block protection is configured through the lock register (see section 5.4: lock register ). the program commands referred to in the following sections must be used according to all the program command timings listed here: ? figure 16.: write enable controlled program waveforms (8-bit mode) , ? figure 17.: write enable controlled program waveforms (16-bit mode) , ? figure 18.: chip enable controlled program waveforms (8-bit mode) , ? figure 19.: chip enable controlled program waveforms (16-bit mode) . 6.4.1 lock register command set the m29w256gl and m29w256gh offer a set of commands to access the lock register and to configure and verify its content. see the following sections in conjunction with section 5.4: lock register , ta bl e 1 9 and tab l e 20 . enter lock register command set command three bus write cycles are required to issue the enter lock register command set command. once the command has been issued, all bus read or program operations are issued to the lock register. an exit protection command set command must then be issued to return the device to read mode (see section 6.4.7: exit protection command set command ). lock register program and lock register read command the lock register program command allows to configure the lock register. the programmed data can then be checked by issuing a lock register read command. 6.4.2 extended memory block the m29w256gh/l has one extra 128-word block (extended memory block). that can only be accessed using the enter extended memory block command. the extended memory block cannot be erased, and is one-time programmable (otp) memory. in extended block mode, erase, chip erase, erase suspend and erase resume commands are not allowed. to exit from the extended memory block mode the exit extended memory block command must be issued.
command interface m29w256gh, m29w256gl 44/98 the device remains in extended memory block mode until the exit extended memory block command is issued or power is removed from the device. after power-up or an hardware reset, the device reverts to read mode, and the commands issued to block 0 addresses will properly address block 0. the extended memory block can be protected by setting the extended memory block protection bit to '0' (see section 5.4: lock register ); however once protected the protection cannot be undone. note: when the device is in the extended memory block mode, the vpp/wp pin cannot be used for fast programming and the unlock bypass mode is not available (see section 2.8: vpp/write protect (vpp/wp)). enter extended memory block command the m29w256gh/l has one extra 128-word block (extended memory block) that can only be accessed using the enter extended memory block command. three bus write cycles are required to issue the extended memory block command. once the command has been issued the device enters the extended memory block mode where all bus read or program operations are conducted on the extended memory block. once the device is in the extended block mode, the extended memory block is addressed by using the addresses occupied by block 0 in the other operating modes (see table 37: block addresses 0 - 127 ). the device remains in extended memory block mode until the exit extended memory block command is issued or power is removed from the device. after power-up or a hardware reset, the device reverts to read mode, and the commands issued to block 0 addresses will properly address block 0. the extended memory block cannot be erased, and can be treated as one-time programmable (otp) memory. in extended block mode, erase, chip erase, erase suspend and erase resume commands are not allowed. to exit from the extended memory block mode the exit extended memory block command must be issued. the extended memory block can be protected by setting the extended memory block protection bit to ?1? (see section 5.4: lock register ); however once protected the protection cannot be undone. note: when the device is in the extended memory block mode, the v pp /wp pin cannot be used for fast programming and the unlock bypass mode is not available (see section 2.8: vpp/write protect (vpp/wp) ). exit extended memory block command the exit extended memory block command is used to exit from the extended memory block mode and return the device to read mode. four bus write operations are required to issue the command.
m29w256gh, m29w256gl command interface 45/98 6.4.3 volatile protection mode command set enter volatile protection command set command three bus write cycles are required to issue the enter volatile protection command set command. once the command has been issued, only the commands related to the volatile protection mode and the exit protection command set can be issued to the device. volatile protection bit program command (vpb program) the vpb program command individually sets a vpb to ?0? for a given block. if the nvpb for the same block is set, the block is locked regardless of the value of the vpb bit. (see table 11: block protection status ). read vpb status command the status of a vpb for a given block can be read by issuing a read vpb status command along with the block address. vpb clear command the vpb clear command individually clears (sets to ?1?) the vpb for a given block. if the nvpb for the same block is set, the block is locked regardless of the value of the vpb bit (see table 11: block protection status ). 6.4.4 non-volatile protection mode command set enter non-volatile protection command set command three bus write cycles are required to issue the enter non-volatile protection command set command. once the command has been issued, only the commands related to the non- volatile protection mode and the exit protection command set can be issued to the device. non-volatile protection bit program command (nvpb program) a block can be protected from program or erase by issuing a non-volatile protection bit command along with the block address. this command sets the nvpb to ?0? for a given block. the non-volatile bit program command is a special kind of program command and must be used according to all the program command timings. the result from this command can be verified by checking the status register. read non-volatile protection bit status command (read nvpb status) the status of a nvpb for a given block or group of blocks can be read by issuing a read non-volatile modify protection bit command along with the block address. clear all non-volatile protection bits command (clear all nvpbs) the nvpbs are erased simultaneously by issuing a clear all non-volatile protection bits command. no specific block address is required. if the nvpb lock bit is set to ?0?, the command fails.
command interface m29w256gh, m29w256gl 46/98 figure 7. nvpb program/erase algorithm ai14242 yes dq6= toggle no yes no enter nvpb command set. program nvpb addr = bad read byte twice addr = bad dq5=1 read byte twice addr = bad no yes wait 500 s dq6= toggle read byte twice addr = bad fail reset pass dq0= '1'(erase) '0'(program) no exit nvpb command set
m29w256gh, m29w256gl command interface 47/98 6.4.5 nvpb lock bit command set enter nvpb lock bit command set command three bus write cycles are required to issue the enter nvpb lock bit command set command. once the command has been issued, the only commands allowing to set the nvpb lock bit and the exit protection command set can be issued to the device. any other command is ignored. see section 5.2.2: non-volatile protection bit lock bit . nvpb lock bit program command this command is used to set the nvpb lock bit to ?0? thus locking the nvpbs, and preventing them from being modified. read nvpb lock bit status command this command is used to read the status of the nvpb lock bit. 6.4.6 password protection mode command set the device accepts the commands belonging to the password protection mode commands set if and only if the password protection mode lock bit (dq2) has been set to '0', (see section section 5.4.3: password protection mode lock bit (dq2) ) otherwise the password commands are ignored. enter password protection command set command three bus write cycles are required to issue the enter password protection command set command. once the command has been issued, only the commands related to the password protection mode and the exit protection command set can be issued to the device. any other command is ignored. password program command the password program command is used to program the 64-bit password used in the password protection mode. to program the 64-bit password, the complete command sequence must be entered eight times at eight consecutive addresses selected by a1-a0 plus dq15a-1 in 8-bit mode, or four times at four consecutive addresses selected by a1-a0 in 16-bit mode. the password program command is a special kind of program command and must be used according to all the program command timings. the result from this command can be verified by checking the status register. the password can be checked by issuing a password read command. once password program operation has completed, an exit protection command set command must be issued to return the device to read mode. the password protection mode can then be selected. by default, all password bits are set to ?1?. password read command the password read command is used to verify the password used in password protection mode.
command interface m29w256gh, m29w256gl 48/98 to verify the 64-bit password, the complete command sequence must be entered eight times at eight consecutive addresses selected by a1-a0 plus dq15a-1 in 8-bit mode, or four times at four consecutive addresses selected by a1-a0 in 16-bit mode. if the password mode lock bit is programmed and the user attempts to read the password, the device will output ffh onto the i/o data bus. an exit protection command set command must be issued to return the device to read mode. password unlock command the password unlock command is used to clear the nvpb lock bit allowing to modify the nvpbs. the password unlock command must be issued along with the correct password. there must be a 1 s delay between successive password unlock commands in order to prevent hackers from cracking the password by trying all possible 64-bit combinations. if this delay is not respected, the latest command will be ignored. approximately 1 s is required for unlocking the device after the valid 64-bit password has been provided. 6.4.7 exit protection command set command the exit protection command set command is used to exit from the lock register, password protection, non-volatile protection, volatile protection, and nvpb lock bit command set mode. it returns the device to read mode.
m29w256gh, m29w256gl command interface 49/98 table 19. block protection commands, 8-bit mode (1)(2)(3) command length bus operations 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th ad data ad data ad data ad data ad data ad data ad data ad data ad data ad data ad data lock register enter lock register command set (4) 3 aaa aa 555 55 aaa 40 lock register program 2x a0 x data (5) lock register read 1 x data (5) volatile protection enter volatile protection command set 3 aaa aa 555 55 aaa e0 vpb program (8) 2 x a0 bad 00 read vpb status 1 x rd(0) vpb clear (8) 2 x a0 bad 01 non-volatile protection enter non- volatile protection command set (4) 3 aaa aa 555 55 aaa c0 nvpb program (6) 2 x a0 bad 00 clear all nvpbs (7) 2 x 80 00 30 read nvpb status (8) 1 bad rd(0) nvpb lock bit enter nvpb lock bit command set 3 aaa aa 555 55 aaa 50 nvpb lock bit program (8) 2x a0 x 00 read nvpb lock bit status (8) 1 x rd(0) password protection enter password protection command set (4) 3 aaa aa 555 55 aaa 60 password program (8)(9) 2x a0 pwa n pwd n password read 8 00 pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 04 pwd 4 05 pwd 5 06 pwd 6 07 pwd 7 password unlock (7) 1 1 00 25 00 03 00 pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 04 pwd 4 05 pwd 5 06 pwd 6 07 pwd 7 00 29 exit protection command set (10) 2x 90 x 00 enter extended block (4) 3 aaa aa 555 55 aaa 88 exit extended block 4 aaa aa 555 55 aaa 90 x 00
command interface m29w256gh, m29w256gl 50/98 1. ad address, dat data, bad any address in the block, rd read data, pwdn password byte 0 to 7, pwan password address (n = 0 to 7), x don?t care. all values in the table are in hexadecimal. 2. grey cells represent read cycles. the other cells are write cycles. 3. dq15 to dq8 are ?don?t care? during unlock and command cycles. a23 to a16 are ?don?t care? during unlock and command cycles u nless an address is required. 4. an enter command sequence must be issued prior to any operation. it disables read and write operations from and to block 0. r ead and write operations from any other block are allowed. 5. data = lock register content. 6. protected and unprotected states correspond to 00 and 01, respectively. 7. the clear all nvpbs comm and programs all nvpbs before erasure in order to prevent the over-erasure of previously cleared non volatile modify protection bits. 8. only one portion of password can be programmed or read by each password program command. 9. the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read. 10. if an entry command set command is issued, an exit protection command set command must be issued to return the device to rea d mode.
m29w256gh, m29w256gl command interface 51/98 table 20. block protection commands, 16-bit mode (1)(2)(3) command length bus operations 1st 2nd 3rd 4th 5th 6th 7th ad data ad data ad data ad data ad data ad data ad data lock register enter lock register command set (4) 3 555 aa 2aa 55 555 40 lock register program 2 x a0 x data (5) lock register read 1 x data (5) volatile protection enter volatile protection command set 3 555 aa 2aa 55 555 e0 vpb program 2 x a0 bad 00 read vpb status 1 x rd(0) vpb clear 2 x a0 bad 01 non-volatile protection enter non-volatile protection command set (4) 3 555 aa 2aa 55 555 c0 nvpb program (6) 2 x a0 bad 00 clear all nvpbs (7) 2 x 80 00 30 read nvpb status 1 bad rd(0) nvpb lock bit enter nvpb lock bit command set 3 555 aa 2aa 55 555 50 nvpb lock bit program 2 x a0 x 00 read nvpb lock bit status 1 x rd(0) password protection enter password protection command set (4) 3 555 aa 2aa 55 555 60 password program (8)(9) 2 x a0 pwan pwdn password read 4 00 pwd0 01 pwd1 02 pwd2 03 pwd3 password unlock (7) 7 00 25 00 03 00 pwd0 01 pwd1 02 pwd2 03 pwd3 00 29 exit protection command set (10) 2x 90 x 00 enter extended block (4) 3 555 aa 2aa 55 555 88 exit extended block 4 555 aa 2aa 55 555 90 x 00 1. ad address, dat data, bad any address in the block, rd read data, pwdn password word 0 to 3, pwan password address (n = 0 to 3), x don?t care. all values in the table are in hexadecimal. 2. grey cells represent read cycles. the other cells are write cycles. 3. dq15 to dq8 are ?don?t care? during unlock and command cycles. a23 to a16 are ?don?t care? during unlock and command cycles u nless an address is required. 4. an enter command sequence must be issued prior to any operation. it disables read and write operations from and to block 0. r ead and write operations from any other block are allowed. 5. data = lock register content. 6. protected and unprotected states correspond to 00 and 01, respectively. 7. the clear all nvpbs command programs all nvpbs before erasure in order to prevent the over-erasure of previously cleared non- volatile modify protection bits. 8. only one portion of password can be programmed or read by each password program command. 9. the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read. 10. if an entry command set command is issued, an exit protection command set command must be issued to return the device to rea d mode.
command interface m29w256gh, m29w256gl 52/98 table 21. program, erase times and program, erase endurance cycles parameter min typ (1)(2) max (2) unit chip erase 40 400 (3) s block erase (128 kbytes) (4) 0.5 s erase suspend latency time 25 35 s block erase timeout 50 s byte program single byte program 16 200 (3) s write to buffer program (64 bytes at-a-time) v pp /wp =v pph 51 s v pp /wp =v ih 78 word program single word program 16 200 (3) s write to buffer program (32 words at-a-time) v pp /wp =v pph 51 s v pp /wp =v ih 78 chip program (byte by byte) 270 800 (3) s chip program (word by word) 135 400 (3) s chip program (write to buffer program) (5) 20 200 (3) s chip program (write to buffer program with v pp /wp =v pph ) (5) 13 50 (3) s chip program (enhanced buffered program) (5) 840s chip program (enhanced buffered program with v pp /wp =v pp ) (5) 525s program suspend latency time 5 15 s program/erase cycles (per block) 100,000 cycles data retention 20 years 1. typical values measured at room temperature and nominal voltages and for not cycled devices. 2. sampled, but not 100% tested. 3. maximum value measured at worst case conditions for both temperature and v cc after 100,000 program/erase cycles. 4. block erase polling cycle time (see figure 24: data polling ac waveforms ). 5. intrinsic program timing, that means without the time requi red to execute the bus cycles to load the program commands.
m29w256gh, m29w256gl status register 53/98 7 status register the m29w256gh/l has one status register. the various bits convey information and errors on the current and previous program/erase operation. bus read operations from any address within the memory, always read the status register during program and erase operations. it is also read during erase suspend when an address within a block being erased is accessed. the bits in the status register are summarized in table 22: status register bits . 7.1 data polling bit (dq7) the data polling bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. the data polling bit is output on dq7 when the status register is read. during program operations the data polling bit outputs the complement of the bit being programmed to dq7. after successful completion of the program operation the memory returns to read mode and bus read operations, from the address just programmed, output dq7, not its complement. during erase operations the data polling bit outputs ?0?, the complement of the erased state of dq7. after successful completion of the erase operation the memory returns to read mode. in erase suspend mode the data polling bit will output a ?1? during a bus read operation within a block being erased. the data polling bit will change from ?0? to ?1? when the program/erase controller has suspended the erase operation. figure 8: data polling flowchart , gives an example of how to use the data polling bit. a valid address is the address being programmed or an address within the block being erased. 7.2 toggle bit (dq6) the toggle bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. the toggle bit is output on dq6 when the status register is read. during a program/erase operation the toggle bit changes from ?0? to ?1? to ?0?, etc., with successive bus read operations at any address. after successful completion of the operation the memory returns to read mode. during erase suspend mode the toggle bit will output when addressing a cell within a block being erased. the toggle bit will stop toggling when the program/erase controller has suspended the erase operation. figure 9: data toggle flowchart , gives an example of how to use the toggle bit.
status register m29w256gh, m29w256gl 54/98 7.3 error bit (dq5) the error bit can be used to identify errors detected by the program/erase controller. the error bit is set to ?1? when a program, block erase or chip erase operation fails to write the correct data to the memory. if the error bit is set a read/reset command must be issued before other commands are issued. the error bit is output on dq5 when the status register is read. note that the program command cannot change a bit set to ?0? back to ?1? and attempting to do so will set dq5 to ?1?. a bus read operation to that address will show the bit is still ?0?. one of the erase commands must be used to set all the bits in a block or in the whole memory from ?0? to ?1?. 7.4 erase timer bit (dq3) the erase timer bit can be used to identify the start of program/erase controller operation during a block erase command. once the program/erase controller starts erasing the erase timer bit is set to ?1?. before the program/erase controller starts the erase timer bit is set to ?0? and additional blocks to be erased may be written to the command interface. the erase timer bit is output on dq3 when the status register is read. 7.5 alternative toggle bit (dq2) the alternative toggle bit can be used to monitor the program/erase controller during erase operations. the alternative toggle bit is output on dq2 when the status register is read. during chip erase and block erase operations the toggle bit changes from ?0? to ?1? to ?0?, etc., with successive bus read operations from addresses within the blocks being erased. a protected block is treated the same as a block not being erased. once the operation completes the memory returns to read mode. during erase suspend the alternative toggle bit changes from ?0? to ?1? to ?0?, etc. with successive bus read operations from addresses within the blocks being erased. bus read operations to addresses within blocks not being erased will output the memory array data as if in read mode. after an erase operation that causes the error bit to be set, the alternative toggle bit can be used to identify which block or blocks have caused the error. the alternative toggle bit changes from ?0? to ?1? to ?0?, etc. with successive bus read operations from addresses within blocks that have not erased correctly. the alternative toggle bit does not change if the addressed block has erased correctly. 7.6 buffered program abort bit (dq1) the buffered program abort bit, dq1, is set to ?1? when a write to buffer program or enhanced buffered program operation aborts. the buffered program abort reset command must be issued to return the device to read mode (see buffered program abort reset command and enhanced buffered program abort reset command in section 6.3: fast program commands ).
m29w256gh, m29w256gl status register 55/98 table 22. status register bits (1) 1. unspecified data bits should be ignored. operation address dq7 dq6 dq5 dq3 dq2 dq1 rb program any address dq7 tog gle 0 ? ? 0 0 program during erase suspend any address dq7 tog gle 0 ? ? ? 0 enhanced buffered program entry any address - toggle 0 - - - 0 buffered program abort any address dq7 tog gle 0 ? ? 1 0 program error any address dq7 toggle 1 ? ? ? hi-z chip erase any address 0 toggle 0 1 toggle ? 0 block erase before timeout erasing block 0 toggle 0 0 toggle ? 0 non-erasing block 0 toggle 0 0 no toggle ?0 block erase erasing block 0 toggle 0 1 toggle ? 0 non-erasing block 0 toggle 0 1 no toggle ?0 erase suspend erasing block 1 no tog gle 0?toggle?hi-z non-erasing block data read as normal ? hi-z erase error good block address 0 toggle 1 1 no toggle ?hi-z faulty block address 0 toggle 1 1 toggle ? hi-z
status register m29w256gh, m29w256gl 56/98 figure 8. data polling flowchart read dq5 & dq7 at valid address start read dq7 at valid address fail pass ai07760 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no
m29w256gh, m29w256gl status register 57/98 figure 9. data toggle flowchart read dq6 at valid address start read dq6 twice at valid address fail pass ai11530 dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle read dq5 & dq6 at valid address
maximum ratings m29w256gh, m29w256gl 58/98 8 maximum ratings stressing the device above the rating listed in table 23: absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. table 23. absolute maximum ratings symbol parameter min max unit t bias temperature under bias ? 50 125 c t stg storage temperature ? 65 150 c v io input or output voltage (1)(2) 1. minimum voltage may undershoot to ? 2 v during transition and for less than 20 ns during transitions. 2. maximum voltage may overshoot to v cc + 2 v during transition and for less than 20 ns during transitions. ? 0.6 v cc +0.6 v v cc supply voltage ? 0.6 4 v v ccq input/output supply voltage ? 0.6 4 v v id identification voltage ? 0.6 13.5 v v pph (3) 3. v pph must not remain at 12 v for more than a total of 80 hrs. program voltage ? 0.6 13.5 v
m29w256gh, m29w256gl dc and ac parameters 59/98 9 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 24: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 10. ac measurement load circuit table 24. operating and ac measurement conditions parameter m29w256gh, m29w256gl unit 70 or 60 (1) ns 1. only available upon customer request. 80 ns min max min max v cc supply voltage 2.7 3.6 2.7 3.6 v v ccq supply voltage (v ccq v cc ) 2.7 3.6 1.65 3.6 v ambient operating temperature (temperature range 1) 070 0 70c ambient operating temperature (temperature range 6) ? 40 85 ? 40 85 c load capacitance (c l )3030pf input rise and fall times 10 10 ns input pulse voltages 0 to v ccq 0 to v ccq v input and output timing ref. voltages v ccq /2 v ccq /2 v ai05558b c l c l includes jig capacitance device under test 25 k v ccq 25 k v cc 0.1 f v pp 0.1 f
dc and ac parameters m29w256gh, m29w256gl 60/98 figure 11. ac measurement i/o waveform figure 12. power-up waiting timings ai05557b v ccq 0 v v ccq /2 table 25. power-up waiting timings symbol parameter m29w256gh, m29w256gl unit 70 or 60 (1) ns 80 ns t vchel v cc (2) high to chip enable low min 55 s t vcqhel v ccq (2) high to chip enable low min 55 s t vchwl v cc high to write enable low min 500 s t vcqhwl v ccq high to write enable low min 500 s 1. only available upon customer request. 2. v cc and v ccq ramps must be synchronized during power-up. ai14247 v cc t vcqhel e v ccq t vcqhwl w t vchel t vchwl
m29w256gh, m29w256gl dc and ac parameters 61/98 table 26. device capacitance (1) symbol parameter test condition min max unit c in input capacitance v in = 0 v 6 pf c out output capacitance v out = 0 v 12 pf 1. sampled only, not 100% tested. table 27. dc characteristics symbol parameter test condition min typ max unit i li (1) input leakage current 0 v v in v cc 1 a i lo output leakage current 0 v v out v cc 1 a i cc1 read current random read e =v il , g =v ih , f=6mhz 10 ma page read e =v il , g =v ih , f=10mhz 15 ma i cc2 supply current (standby) e =v ccq 0.2v, rp =v ccq 0.2v 100 a i cc3 (2) supply current (program/erase) program/erase controller active v pp /wp = v il or v ih 20 ma v pp /wp =v pph 20 ma i pp1 program current (program) read or standby v pp /wp v cc 15 a i pp2 reset rp =v ss 0.2v 1 5 a i pp3 program operation ongoing v pp /wp =12v5% 1 10 ma v pp /wp =v cc 15 a i pp4 program current (erase) erase operation ongoing v pp /wp =12v5% 3 10 ma v pp /wp =v cc 15 a v il input low voltage v cc 2.7 v ? 0.5 0.3v ccq v v ih input high voltage v cc 2.7 v 0.7v ccq v ccq +0.4 v v ol output low voltage i ol =100 a, v cc =v cc(min) , v ccq =v ccq(min) 0.15v ccq v v oh output high voltage i oh =100 a, v cc =v cc(min) , v ccq =v ccq(min) 0.85v ccq v v id identification voltage 11.5 12.5 v v pph voltage for v pp /wp program acceleration 11.5 12.5 v v lko (2) program/erase lockout supply voltage 1.8 2.5 v 1. the maximum input leakage current is 5 a on the v pp /wp pin. 2. sampled only, not 100% tested.
dc and ac parameters m29w256gh, m29w256gl 62/98 figure 13. random read ac waveforms (8-bit mode) note: byte = v il figure 14. random read ac waveforms (16-bit mode) note: byte = v ih ai08970 tavav tavqv taxqx telqx tehqz tglqv tglqx tghqx valid a0-a23/ a?1 g dq0-dq7 e telqv tehqx tghqz valid tbhqv t elbl/ t elbh t blqz byte (8-bit mode) ai13698 tavav tavqv taxqx telqx tehqz tglqv tglqx tghqx valid a0-a23 g dq0-dq14, dq15a?1 e telqv tehqx tghqz valid tbhqv t elbl/ t elbh t blqz byte (8-bit mode)
m29w256gh, m29w256gl dc and ac parameters 63/98 figure 15. page read ac waveforms (16-bit mode) ai08971 c tehqz tghqx valid a3-a23 g dq0-dq15 dq15a-1 e telqv tehqx tghqz valid a0-a2 valid valid valid valid valid valid valid tglqv tavqv t avqv1 valid valid valid valid valid valid valid valid
dc and ac parameters m29w256gh, m29w256gl 64/98 table 28. read ac characteristics symbol alt. parameter test condition m29w256gh, m29w256gl unit 60 ns (1) v ccq =v cc 70 ns v ccq =v cc 80 ns v ccq =1.65 v to v cc t avav t rc address valid to next address valid e =v il , g =v il min 60 70 80 ns t avqv t acc address valid to output valid e =v il , g =v il max 60 70 80 ns t avqv1 t page address valid to output valid (page) e =v il , g =v il max 25 25 30 ns t elqx (2) t lz chip enable low to output transition g =v il min 0 0 0 ns t elqv t e chip enable low to output valid g =v il max 60 70 80 ns t glqx (2) t olz output enable low to output transition e =v il min 0 0 0 ns t glqv t oe output enable low to output valid e =v il max 25 25 30 ns t ehqz (2) t hz chip enable high to output hi-z g =v il max 20 20 30 ns t ghqz (2) t df output enable high to output hi-z e =v il max 20 20 20 ns t ehqx t ghqx t axqx t oh chip enable, output enable or address transition to output transition min 0 0 0 ns t elbl t elbh t elfl t elfh chip enable to byte low or high max 5 5 5 ns t blqz t flqz byte low to output hi-z max 25 25 25 ns t bhqv t fhqv byte high to output valid max 30 30 30 ns 1. only available upon customer request. 2. sampled only, not 100% tested.
m29w256gh, m29w256gl dc and ac parameters 65/98 figure 16. write enable controlled program waveforms (8-bit mode) 1. only the third and fourth cycles of the program command are represented. the program command is followed by the check of status register data polling bit and by a read operati on that outputs the data, dout, programmed by the previous program command. 2. pa is the address of the memory location to be programmed. pd is the data to be programmed. 3. dq7 is the complement of the data bit being programmed to dq7 (see section 7.1: data polling bit (dq7) ). 4. see table 29: write ac characterist ics, write enable controlled , table 30: write ac characteristics, chip enable controlled and table 28: read ac characteristics for details on the timings. ai13333 g w a0-a23 dq0-dq7 e 555h aoh pa pa 3rd cycle 4t h cycle pd dq7 d out d out tavav tavav tavwl twlax data polling read cycle telwl twheh telqv tghwl twlwh twhwl twhwh1 tglqv tdvwh twhdx tghqz taxqx a-1
dc and ac parameters m29w256gh, m29w256gl 66/98 figure 17. write enable controlled program waveforms (16-bit mode) 1. only the third and fourth cycles of the program command are represented. the program command is followed by the check of status register data polling bit and by a read operati on that outputs the data, dout, programmed by the previous program command. 2. pa is the address of the memory location to be programmed. pd is the data to be programmed. 3. dq7 is the complement of the data bit being programmed to dq7 (see section 7.1: data polling bit (dq7) ). 4. see table 29: write ac characterist ics, write enable controlled , table 30: write ac characteristics, chip enable controlled and table 28: read ac characteristics for details on the timings. ai13699 g w a0-a23 dq0-dq1', dq15a?1 e 555h aoh pa pa 3rd cycle 4t h cycle pd dq7 d out d out tavav tavav tavwl twlax data polling read cycle telwl twheh telqv tghwl twlwh twhwl twhwh1 tglqv tdvwh twhdx tghqz taxqx
m29w256gh, m29w256gl dc and ac parameters 67/98 m table 29. write ac characteristics, write enable controlled symbol alt parameter m29w256gh, m29w256gl unit 60 ns (1) 70 ns 80 ns t avav t wc address valid to next address valid min 65 70 80 ns t elwl t cs chip enable low to write enable low min 0 0 0 ns t wlwh t wp write enable low to write enable high min 35 35 35 ns t dvwh t ds input valid to write enable high min 45 45 45 ns t whdx t dh write enable high to input transition min 0 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 0 ns t whwl t wph write enable high to write enable low min 30 30 30 ns t avwl t as address valid to write enable low min 0 0 0 ns t wlax t ah write enable low to address transition min 45 45 45 ns t ghwl output enable high to write enable low min 0 0 0 ns t whgl t oeh write enable high to output enable low min 0 0 0 ns t whrl (2) t busy program/erase valid to rb low max 30 30 30 ns t vchel t vcs v cc high to chip enable low min 50 50 50 s 1. only available upon customer request. 2. sampled only, not 100% tested.
dc and ac parameters m29w256gh, m29w256gl 68/98 figure 18. chip enable controlled program waveforms (8-bit mode) 1. only the third and fourth cycles of the program command are represented. the program command is followed by the check of status register data polling bit. 2. pa is the address of the memory location to be programmed. pd is the data to be programmed. 3. dq7 is the complement of the data bit being programmed to dq7 (see section 7.1: data polling bit (dq7) ). 4. see table 29: write ac characteristics, write enable controlled , table 30: write ac characteristics, chip enable controlled and table 28: read ac characteristics for details on the timings. ai13334 g e a0-a23/ a?1 dq0-dq7 w 555h aoh pa pa 3rd cycle 4t h cycle pd dq7 d out tavav tavel telax data polling twlel tehwh tghel teleh tehel1 twhwh1 tdveh tehdx
m29w256gh, m29w256gl dc and ac parameters 69/98 figure 19. chip enable controlled program waveforms (16-bit mode) 1. only the third and fourth cycles of the program command are represented. the program command is followed by the check of status register data polling bit. 2. pa is the address of the memory location to be programmed. pd is the data to be programmed. 3. dq7 is the complement of the data bit being programmed to dq7 (see section 7.1: data polling bit (dq7) ). 4. see table 29: write ac characteristics, write enable controlled , table 30: write ac characteristics, chip enable controlled and table 28: read ac characteristics for details on the timings. ai14100 g e a0-a23 dq0-dq14 a?1 w 555h aoh pa pa 3rd cycle 4t h cycle pd dq7 d out tavav tavel telax data polling twlel tehwh tghel teleh tehel1 twhwh1 tdveh tehdx
dc and ac parameters m29w256gh, m29w256gl 70/98 figure 20. chip/block erase waveforms (8-bit mode) 1. for a chip erase command, addresses and data are 555h and 10h, respectively, while they are bad and 30h for a block erase command. 2. bad is the block address. 3. see table 29: write ac characteristics, write enable controlled , table 30: write ac characteristics, chip enable controlled and table 28: read ac characteristics for details on the timings. ai13335 g w a0-a23/ a?1 dq0-dq7 e 555h aah 2aah 555h 55h 80h aah tavav tavwl twlax telwl twheh tghwl twlwh twhwl tdvwh twhdx 555h 2aah 555h/ bad (1) 55h 10h/ 30h table 30. write ac characteristics, chip enable controlled symbol alt. parameter m29w256gh, m29w256gl unit 60 ns (1) 70 ns 80 ns t avav t wc address valid to next address valid min 65 70 80 ns t wlel t ws write enable low to chip enable low min 0 0 0 ns t eleh t cp chip enable low to chip enable high min 35 35 35 ns t dveh t ds input valid to chip enable high min 45 45 45 ns t ehdx t dh chip enable high to input transition min 0 0 0 ns t ehwh t wh chip enable high to write enable high min 0 0 0 ns t ehel t cph chip enable high to chip enable low min 30 30 30 ns t avel t as address valid to chip enable low min 0 0 0 ns t elax t ah chip enable low to address transition min 45 45 45 ns t ghel output enable high chip enable low min 0 0 0 ns 1. only available upon customer request.
m29w256gh, m29w256gl dc and ac parameters 71/98 figure 21. reset ac waveforms (no program/erase ongoing) figure 22. reset during program/erase operation ac waveforms ai11300c rb rp tplpx tphel, tphgl tphwl e, g, w ai11301c rb rp tplpx trhel, trhgl, trhwl e, g, tplyh w table 31. reset ac characteristics symbol alt. parameter m29w256gh, m29w256gl unit 60 (1) ns 70 ns 80 ns t plyh (2) t read y rp low to read mode, during program or erase max 50 50 50 s t plpx t rp rp pulse width min 10 10 10 s t phel, t phgl, t phwl (2) t rh rp high to write enable low, chip enable low, output enable low min 50 50 50 ns t rpd rp low to standby mode, during read mode min 10 10 10 s rp low to standby mode, during program or erase min 50 50 50 s t rhel, t rhgl, t rhwl (2) t rb rb high to write enable low, chip enable low, output enable low min 0 0 0 ns 1. only available upon customer request. 2. sampled only, not 100% tested.
dc and ac parameters m29w256gh, m29w256gl 72/98 figure 23. accelerated program timing waveforms figure 24. data polling ac waveforms 1. dq7 returns valid data bit when the ongoing program or erase command is completed. 2. see table 32: accelerated program and data polling/data toggle ac characteristics and table 28: read ac characteristics for details on the timings. ai05563 v pp /wp v pph v il or v ih tvhvpp tvhvpp ai13336c g e dq7 w dq7 dq7= valid data dq6-dq0 dq6-dq0= output flag data data dq6-dq0= valid data hi-z hi-z r/b twheh tglqv tehqz tghqz twhgl2 telqv twhwh1 or twhwh2 twhrl
m29w256gh, m29w256gl dc and ac parameters 73/98 figure 25. toggle/alternative toggle bit polling ac waveforms (8-bit mode) 1. dq6 stops toggling when the ongoing program or erase command is completed. dq2 stops toggling when the ongoing chip erase or block erase command is completed. 2. see table 32: accelerated program and data polling/data toggle ac characteristics and table 28: read ac characteristics for details on the timings. ai13337 w e g a0-a23/ a?1 dq6/ dq2 toggle toggle toggle st o p toggling out p ut val i d tghax taxgl tehax tavel tehel2 twhgl2 tghgl2 tghgl2 dat a r/ b twhdx tglqv telqv twhrl table 32. accelerated program and data polling/data toggle ac characteristics symbol alt parameter m29w256gh, m29w256gl unit 60 (1) ns 70 ns 80 ns t vhvpp v pp /wp raising and falling time min 250 250 250 ns t axgl t aso address setup time to output enable low during toggle bit polling min 10 10 10 ns t ghax, t ehax t aht address hold time from output enable during toggle bit polling min 10 10 10 ns t ehel2 t eph chip enable high during toggle bit polling min 10 10 10 ns t whgl2, t ghgl2 t oeh output hold time during data and toggle bit polling min 20 20 20 ns t whrl t busy program/erase valid to rb low max 30 30 30 ns 1. only available upon customer request.
package mechanical m29w256gh, m29w256gl 74/98 10 package mechanical in order to meet environmental requirements, numonyx offers these devices in rohs compliant packages. rohs compliant packages are lead-free. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. figure 26. tsop56 ? 56 lead plastic thin small outline, 14 x 20 mm, package outline 1. drawing is not to scale. table 33. tsop56 ? 56 lead plastic thin small outline, 14 x 20 mm, package mechanical data symbol millimeters inches typ min max typ min max a??1.20??0.047 a1 0.10 0.05 0.15 0.004 0.002 0.006 a2 1.00 0.95 1.05 0.039 0.037 0.041 b 0.22 0.17 0.27 0.009 0.007 0.011 c ? 0.10 0.21 ? 0.004 0.008 cp ? ? 0.10 ? ? 0.004 d1 14.00 13.90 14.10 0.551 0.547 0.555 e 20.00 19.80 20.20 0.787 0.780 0.795 e1 18.40 18.30 18.50 0.724 0.720 0.728 e 0.50 ? ? 0.020 ? ? l 0.60 0.50 0.70 0.024 0.020 0.028 30 530 5 tsop-k b e die c l a1 e1 e a a2 28 1 56 29 d1 l1 cp
m29w256gh, m29w256gl package mechanical 75/98 figure 27. tbga64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package outline 1. drawing is not to scale. table 34. tbga64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a? ?1.20? ?0.047 a1 0.30 0.20 0.35 0.012 0.008 0.014 a2 0.80 ? ? 0.031 ? ? b ? 0.35 0.50 ? 0.014 0.020 d 10.00 9.90 10.10 0.394 0.390 0.398 d1 7.000 ? ? 0.276 ? ? ddd ? ? 0.10 ? ? 0.004 e 1.00 ? ? 0.039 ? ? e 13.00 12.90 13.10 0.512 0.508 0.516 e1 7.00 ? ? 0.276 ? ? fd 1.50 ? ? 0.059 ? ? fe 3.00 ? ? 0.118 ? ? sd 0.50 ? ? 0.020 ? ? se 0.50 ? ? 0.020 ? ? e1 e d1 d eb sd se a2 a1 a bga-z23 ddd fd fe ball "a1"
package mechanical m29w256gh, m29w256gl 76/98 figure 28. lbga64 11 x 13 mm?8 x 8 active ball array, 1 mm pitch, package outline 1. drawing is not to scale. table 35. lbga64 11 x 13 mm?8 x 8 active ball array, 1 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a? ?1.40? ?0.055 a1 0.48 0.43 0.53 0.018 0.016 a2 0.80 ? ? 0.031 ? ? b ? 0.55 0.65 ? 0.021 0.025 d 11.00 10.90 11.10 0.433 0.429 0.437 d1 7.00 ? ? 0.275 ? ? ddd ? ? 0.15 ? ? 0.0059 e 1.00 ? ? 0.039 ? ? e 13.0 12.90 13.10 0.511 0.507 0.515 e1 7.00 ? ? 0.275 ? ? fd 2.00 ? ? 0.078 ? ? fe 3.00 ? ? 0.118 ? ? sd 0.50 ? ? 0.0196 ? ? se 0.50 ? ? 0.0196 ? ? e1 e d1 d eb sd se a2 a1 a bga-z23 ddd fd fe ball "a1"
m29w256gh, m29w256gl ordering information 77/98 11 ordering information note: this product is also available with the extended memory block factory locked. for further details and ordering information contact your nearest numonyx sales office. devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest numonyx sales office. automotive grade part is qualified and characterized according to aec q100 and q003 or equivalent; advanced screening according to aec q001 and q002 or equivalent. table 36. ordering information scheme example: m29w256gh 70 n 6 f device type m29 operating voltage w = v cc = 2.7 to 3.6 v device function 128gh = 128-mbit (x8/x16), page, uniform block, flash memory, highest block protected by v pp /wp 128gl = 128-mbit (x8/x16), page, uniform block, flash memory, lowest block protected by v pp /wp speed 70 = 70 ns (80 ns if v ccq = 1.65 v to v cc ) 60 = 60 ns (80 ns if v ccq = 1.65 v to v cc ) (1) 1. only available upon customer request. 7a = 70 ns (80 ns if v ccq = 1.65 v to v cc ) automotive qualified (available only with option 6) package n = tsop56: 14 x 20 mm za = tbga64: 10 x 13 mm, 1 mm pitch zs = lbga64: 11 x 13 mm, 1 mm pitch temperature range 1 = 0 to 70 c 6 = ?40 to 85 c option e = rohs compliant package, standard packing f = rohs compliant package, tape & reel packing
block addresses and read/modify protection groups m29w256gh, m29w256gl 78/98 appendix a block addresses and read/modify protection groups table 37 shows block addresses 0-127. ta bl e 3 8 shows block addresses 128-255. table 37. block addresses 0 - 127 (page 1 of 4) block protection group block size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) 0 protection group 128/64 0000000?001ffff 0000000?000ffff 1 protection group 128/64 0020000?003ffff 0010000?001ffff 2 protection group 128/64 0040000?005ffff 0020000?002ffff 3 protection group 128/64 0060000?007ffff 0030000?003ffff 4 protection group 128/64 0080000?009ffff 0040000?004ffff 5 protection group 128/64 00a0000?00bffff 0050000?005ffff 6 protection group 128/64 00c0000?00dffff 0060000?006ffff 7 protection group 128/64 00e0000?00fffff 0070000?007ffff 8 protection group 128/64 0100000?011ffff 0080000?008ffff 9 protection group 128/64 0120000?013ffff 0090000?009ffff 10 protection group 128/64 0140000?015ffff 00a0000?00affff 11 protection group 128/64 0160000?017ffff 00b0000?00bffff 12 protection group 128/64 0180000?019ffff 00c0000?00cffff 13 protection group 128/64 01a0000?01bffff 00d0000?00dffff 14 protection group 128/64 01c0000?01dffff 00e0000?00effff 15 protection group 128/64 01e0000?01fffff 00f0000?00fffff 16 protection group 128/64 0200000?021ffff 0100000?010ffff 17 protection group 128/64 0220000?023ffff 0110000?011ffff 18 protection group 128/64 0240000?025ffff 0120000?012ffff 19 protection group 128/64 0260000?027ffff 0130000?013ffff 20 protection group 128/64 0280000?029ffff 0140000?014ffff 21 protection group 128/64 02a0000?02bffff 0150000?015ffff 22 protection group 128/64 02c0000?02dffff 0160000?016ffff 23 protection group 128/64 02e0000?02fffff 0170000?017ffff 24 protection group 128/64 0300000?031ffff 0180000?018ffff 25 protection group 128/64 0320000?033ffff 0190000?019ffff 26 protection group 128/64 0340000?035ffff 01a0000?01affff 27 protection group 128/64 0360000?037ffff 01b0000?01bffff 28 protection group 128/64 0380000?039ffff 01c0000?01cffff
m29w256gh, m29w256gl block addresses and read/modify protection groups 79/98 29 protection group 128/64 03a0000?03bffff 01d0000?01dffff 30 protection group 128/64 03c0000?03dffff 01e0000?01effff 31 protection group 128/64 03e0000?03fffff 01f0000?01fffff 32 protection group 128/64 0400000?041ffff 0200000?020ffff 33 protection group 128/64 0420000?043ffff 0210000?021ffff 34 protection group 128/64 0440000?045ffff 0220000?022ffff 35 protection group 128/64 0460000?047ffff 0230000?023ffff 36 protection group 128/64 0480000?049ffff 0240000?024ffff 37 protection group 128/64 04a0000?04bffff 0250000?025ffff 38 protection group 128/64 04c0000?04dffff 0260000?026ffff 39 protection group 128/64 04e0000?04fffff 0270000?027ffff 40 protection group 128/64 0500000?051ffff 0280000?028ffff 41 protection group 128/64 0520000?053ffff 0290000?029ffff 42 protection group 128/64 0540000?055ffff 02a0000?02affff 43 protection group 128/64 0560000?057ffff 02b0000?02bffff 44 protection group 128/64 0580000?059ffff 02c0000?02cffff 45 protection group 128/64 05a0000?05bffff 02d0000?02dffff 46 protection group 128/64 05c0000?05dffff 02e0000?02effff 47 protection group 128/64 05e0000?05fffff 02f0000?02fffff 48 protection group 128/64 0600000?061ffff 0300000?030ffff 49 protection group 128/64 0620000?063ffff 0310000?031ffff 50 protection group 128/64 0640000?065ffff 0320000?032ffff 51 protection group 128/64 0660000?067ffff 0330000?033ffff 52 protection group 128/64 0680000?069ffff 0340000?034ffff 53 protection group 128/64 06a0000?06bffff 0350000?035ffff 54 protection group 128/64 06c0000?06dffff 0360000?036ffff 55 protection group 128/64 06e0000?06fffff 0370000?037ffff 56 protection group 128/64 0700000?071ffff 0380000?038ffff 57 protection group 128/64 0720000?073ffff 0390000?039ffff 58 protection group 128/64 0740000?075ffff 03a0000?03affff 59 protection group 128/64 0760000?077ffff 03b0000?03bffff 60 protection group 128/64 0780000?079ffff 03c0000?03cffff 61 protection group 128/64 07a0000?07bffff 03d0000?03dffff table 37. block addresses 0 - 127 (page 2 of 4) block protection group block size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
block addresses and read/modify protection groups m29w256gh, m29w256gl 80/98 62 protection group 128/64 07c0000?07dffff 03e0000?03effff 63 protection group 128/64 07e0000?07fffff 03f0000?03fffff 64 protection group 128/64 0800000?081ffff 0400000?040ffff 65 protection group 128/64 0820000?083ffff 0410000?041ffff 66 protection group 128/64 0840000?085ffff 0420000?042ffff 67 protection group 128/64 0860000?087ffff 0430000?043ffff 68 protection group 128/64 0880000?089ffff 0440000?044ffff 69 protection group 128/64 08a0000?08bffff 0450000?045ffff 70 protection group 128/64 08c0000?08dffff 0460000?046ffff 71 protection group 128/64 08e0000?08fffff 0470000?047ffff 72 protection group 128/64 0900000?091ffff 0480000?048ffff 73 protection group 128/64 0920000?093ffff 0490000?049ffff 74 protection group 128/64 0940000?095ffff 04a0000?04affff 75 protection group 128/64 0960000?097ffff 04b0000?04bffff 76 protection group 128/64 0980000?099ffff 04c0000?04cffff 77 protection group 128/64 09a0000?09bffff 04d0000?04dffff 78 protection group 128/64 09c0000?09dffff 04e0000?04effff 79 protection group 128/64 09e0000?09fffff 04f0000?04fffff 80 protection group 128/64 0a00000?0a1ffff 0500000?050ffff 81 protection group 128/64 0a20000?0a3ffff 0510000?051ffff 82 protection group 128/64 0a40000?0a5ffff 0520000?052ffff 83 protection group 128/64 0a60000?0a7ffff 0530000?053ffff 84 protection group 128/64 0a80000?0a9ffff 0540000?054ffff 85 protection group 128/64 0aa0000?0abffff 0550000?055ffff 86 protection group 128/64 0ac0000?0adffff 0560000?056ffff 87 protection group 128/64 0ae0000?0afffff 0570000?057ffff 88 protection group 128/64 0b00000?0b1ffff 0580000?058ffff 89 protection group 128/64 0b20000?0b3ffff 0590000?059ffff 90 protection group 128/64 0b40000?0b5ffff 05a0000?05affff 91 protection group 128/64 0b60000?0b7ffff 05b0000?05bffff 92 protection group 128/64 0b80000?0b9ffff 05c0000?05cffff 93 protection group 128/64 0ba0000?0bbffff 05d0000?05dffff 94 protection group 128/64 0bc0000?0bdffff 05e0000?05effff table 37. block addresses 0 - 127 (page 3 of 4) block protection group block size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
m29w256gh, m29w256gl block addresses and read/modify protection groups 81/98 95 protection group 128/64 0be0000?0bfffff 05f0000?05fffff 96 protection group 128/64 0c00000?0c1ffff 0600000?060ffff 97 protection group 128/64 0c20000?0c3ffff 0610000?061ffff 98 protection group 128/64 0c40000?0c5ffff 0620000?062ffff 99 protection group 128/64 0c60000?0c7ffff 0630000?063ffff 100 protection group 128/64 0c80000?0c9ffff 0640000?064ffff 101 protection group 128/64 0ca0000?0cbffff 0650000?065ffff 102 protection group 128/64 0cc0000?0cdffff 0660000?066ffff 103 protection group 128/64 0ce0000?0cfffff 0670000?067ffff 104 protection group 128/64 0d00000?0d1ffff 0680000?068ffff 105 protection group 128/64 0d20000?0d3ffff 0690000?069ffff 106 protection group 128/64 0d40000?0d5ffff 06a0000?06affff 107 protection group 128/64 0d60000?0d7ffff 06b0000?06bffff 108 protection group 128/64 0d80000?0d9ffff 06c0000?06cffff 109 protection group 128/64 0da0000?0dbffff 06d0000?06dffff 110 protection group 128/64 0dc0000?0ddffff 06e0000?06effff 111 protection group 128/64 0de0000?0dfffff 06f0000?06fffff 112 protection group 128/64 0e00000?0e1ffff 0700000?070ffff 113 protection group 128/64 0e20000?0e3ffff 0710000?071ffff 114 protection group 128/64 0e40000?0e5ffff 0720000?072ffff 115 protection group 128/64 0e60000?0e7ffff 0730000?073ffff 116 protection group 128/64 0e80000?0e9ffff 0740000?074ffff 117 protection group 128/64 0ea0000?0ebffff 0750000?075ffff 118 protection group 128/64 0ec0000?0edffff 0760000?076ffff 119 protection group 128/64 0ee0000?0efffff 0770000?077ffff 120 protection group 128/64 0f00000?0f1ffff 0780000?078ffff 121 protection group 128/64 0f20000?0f3ffff 0790000?079ffff 122 protection group 128/64 0f40000?0f5ffff 07a0000?07affff 123 protection group 128/64 0f60000?0f7ffff 07b0000?07bffff 124 protection group 128/64 0f80000?0f9ffff 07c0000?07cffff 125 protection group 128/64 0fa0000?0fbffff 07d0000?07dffff 126 protection group 128/64 0fc0000?0fdffff 07e0000?07effff 127 protection group 128/64 0fe0000?0ffffff 07f0000?07fffff table 37. block addresses 0 - 127 (page 4 of 4) block protection group block size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
block addresses and read/modify protection groups m29w256gh, m29w256gl 82/98 table 38. block addresses 128 - 255 (page 1 of 4) 128 128 64 1000000 101ffff 0800000 080ffff 129 128 64 1020000 103ffff 0810000 081ffff 130 128 64 1040000 105ffff 0820000 082ffff 131 128 64 1060000 107ffff 0830000 083ffff 132 128 64 1080000 109ffff 0840000 084ffff 133 128 64 10a0000 10bffff 0850000 085ffff 134 128 64 10c0000 10dffff 0860000 086ffff 135 128 64 10e0000 10fffff 0870000 087ffff 136 128 64 1100000 111ffff 0880000 088ffff 137 128 64 1120000 113ffff 0890000 089ffff 138 128 64 1140000 115ffff 08a0000 08affff 139 128 64 1160000 117ffff 08b0000 08bffff 140 128 64 1180000 119ffff 08c0000 08cffff 141 128 64 11a0000 11bffff 08d0000 08dffff 142 128 64 11c0000 11dffff 08e0000 08effff 143 128 64 11e0000 11fffff 08f0000 08fffff 144 128 64 1200000 121ffff 0900000 090ffff 145 128 64 1220000 123ffff 0910000 091ffff 146 128 64 1240000 125ffff 0920000 092ffff 147 128 64 1260000 127ffff 0930000 093ffff 148 128 64 1280000 129ffff 0940000 094ffff 149 128 64 12a0000 12bffff 0950000 095ffff 150 128 64 12c0000 12dffff 0960000 096ffff 151 128 64 12e0000 12fffff 0970000 097ffff 152 128 64 1300000 131ffff 0980000 098ffff 153 128 64 1320000 133ffff 0990000 099ffff 154 128 64 1340000 135ffff 09a0000 09affff 155 128 64 1360000 137ffff 09b0000 09bffff 156 128 64 1380000 139ffff 09c0000 09cffff 157 128 64 13a0000 13bffff 09d0000 09dffff 158 128 64 13c0000 13dffff 09e0000 09effff 159 128 64 13e0000 13fffff 09f0000 09fffff 160 128 64 1400000 141ffff 0a00000 0a0ffff 161 128 64 1420000 143ffff 0a10000 0a1ffff 162 128 64 1440000 145ffff 0a20000 0a2ffff 163 128 64 1460000 147ffff 0a30000 0a3ffff
m29w256gh, m29w256gl block addresses and read/modify protection groups 83/98 164 128 64 1480000 149ffff 0a40000 0a4ffff 165 128 64 14a0000 14bffff 0a50000 0a5ffff 166 128 64 14c0000 14dffff 0a60000 0a6ffff 167 128 64 14e0000 14fffff 0a70000 0a7ffff 168 128 64 1500000 151ffff 0a80000 0a8ffff 169 128 64 1520000 153ffff 0a90000 0a9ffff 170 128 64 1540000 155ffff 0aa0000 0aaffff 171 128 64 1560000 157ffff 0ab0000 0abffff 172 128 64 1580000 159ffff 0ac0000 0acffff 173 128 64 15a0000 15bffff 0ad0000 0adffff 174 128 64 15c0000 15dffff 0ae0000 0aeffff 175 128 64 15e0000 15fffff 0af0000 0afffff 176 128 64 1600000 161ffff 0b00000 0b0ffff 177 128 64 1620000 163ffff 0b10000 0b1ffff 178 128 64 1640000 165ffff 0b20000 0b2ffff 179 128 64 1660000 167ffff 0b30000 0b3ffff 180 128 64 1680000 169ffff 0b40000 0b4ffff 181 128 64 16a0000 16bffff 0b50000 0b5ffff 182 128 64 16c0000 16dffff 0b60000 0b6ffff 183 128 64 16e0000 16fffff 0b70000 0b7ffff 184 128 64 1700000 171ffff 0b80000 0b8ffff 185 128 64 1720000 173ffff 0b90000 0b9ffff 186 128 64 1740000 175ffff 0ba0000 0baffff 187 128 64 1760000 177ffff 0bb0000 0bbffff 188 128 64 1780000 179ffff 0bc0000 0bcffff 189 128 64 17a0000 17bffff 0bd0000 0bdffff 190 128 64 17c0000 17dffff 0be0000 0beffff 191 128 64 17e0000 17fffff 0bf0000 0bfffff 192 128 64 1800000 181ffff 0c00000 0c0ffff 193 128 64 1820000 183ffff 0c10000 0c1ffff 194 128 64 1840000 185ffff 0c20000 0c2ffff 195 128 64 1860000 187ffff 0c30000 0c3ffff 196 128 64 1880000 189ffff 0c40000 0c4ffff 197 128 64 18a0000 18bffff 0c50000 0c5ffff 198 128 64 18c0000 18dffff 0c60000 0c6ffff 199 128 64 18e0000 18fffff 0c70000 0c7ffff table 38. block addresses 128 - 255 (page 2 of 4)
block addresses and read/modify protection groups m29w256gh, m29w256gl 84/98 200 128 64 1900000 191ffff 0c80000 0c8ffff 201 128 64 1920000 193ffff 0c90000 0c9ffff 202 128 64 1940000 195ffff 0ca0000 0caffff 203 128 64 1960000 197ffff 0cb0000 0cbffff 204 128 64 1980000 199ffff 0cc0000 0ccffff 205 128 64 19a0000 19bffff 0cd0000 0cdffff 206 128 64 19c0000 19dffff 0ce0000 0ceffff 207 128 64 19e0000 19fffff 0cf0000 0cfffff 208 128 64 1a00000 1a1ffff 0d00000 0d0ffff 209 128 64 1a20000 1a3ffff 0d10000 0d1ffff 210 128 64 1a40000 1a5ffff 0d20000 0d2ffff 211 128 64 1a60000 1a7ffff 0d30000 0d3ffff 212 128 64 1a80000 1a9ffff 0d40000 0d4ffff 213 128 64 1aa0000 1abffff 0d50000 0d5ffff 214 128 64 1ac0000 1adffff 0d60000 0d6ffff 215 128 64 1ae0000 1afffff 0d70000 0d7ffff 216 128 64 1b00000 1b1ffff 0d80000 0d8ffff 217 128 64 1b20000 1b3ffff 0d90000 0d9ffff 218 128 64 1b40000 1b5ffff 0da0000 0daffff 219 128 64 1b60000 1b7ffff 0db0000 0dbffff 220 128 64 1b80000 1b9ffff 0dc0000 0dcffff 221 128 64 1ba0000 1bbffff 0dd0000 0ddffff 222 128 64 1bc0000 1bdffff 0de0000 0deffff 223 128 64 1be0000 1bfffff 0df0000 0dfffff 224 128 64 1c00000 1c1ffff 0e00000 0e0ffff 225 128 64 1c20000 1c3ffff 0e10000 0e1ffff 226 128 64 1c40000 1c5ffff 0e20000 0e2ffff 227 128 64 1c60000 1c7ffff 0e30000 0e3ffff 228 128 64 1c80000 1c9ffff 0e40000 0e4ffff 229 128 64 1ca0000 1cbffff 0e50000 0e5ffff 230 128 64 1cc0000 1cdffff 0e60000 0e6ffff 231 128 64 1ce0000 1cfffff 0e70000 0e7ffff 232 128 64 1d00000 1d1ffff 0e80000 0e8ffff 233 128 64 1d20000 1d3ffff 0e90000 0e9ffff 234 128 64 1d40000 1d5ffff 0ea0000 0eaffff 235 128 64 1d60000 1d7ffff 0eb0000 0ebffff table 38. block addresses 128 - 255 (page 3 of 4)
m29w256gh, m29w256gl block addresses and read/modify protection groups 85/98 236 128 64 1d80000 1d9ffff 0ec0000 0ecffff 237 128 64 1da0000 1dbffff 0ed0000 0edffff 238 128 64 1dc0000 1ddffff 0ee0000 0eeffff 239 128 64 1de0000 1dfffff 0ef0000 0efffff 240 128 64 1e00000 1e1ffff 0f00000 0f0ffff 241 128 64 1e20000 1e3ffff 0f10000 0f1ffff 242 128 64 1e40000 1e5ffff 0f20000 0f2ffff 243 128 64 1e60000 1e7ffff 0f30000 0f3ffff 244 128 64 1e80000 1e9ffff 0f40000 0f4ffff 245 128 64 1ea0000 1ebffff 0f50000 0f5ffff 246 128 64 1ec0000 1edffff 0f60000 0f6ffff 247 128 64 1ee0000 1efffff 0f70000 0f7ffff 248 128 64 1f00000 1f1ffff 0f80000 0f8ffff 249 128 64 1f20000 1f3ffff 0f90000 0f9ffff 250 128 64 1f40000 1f5ffff 0fa0000 0faffff 251 128 64 1f60000 1f7ffff 0fb0000 0fbffff 252 128 64 1f80000 1f9ffff 0fc0000 0fcffff 253 128 64 1fa0000 1fbffff 0fd0000 0fdffff 254 128 64 1fc0000 1fdffff 0fe0000 0feffff 255 128 64 1fe0000 1ffffff 0ff0000 0ffffff table 38. block addresses 128 - 255 (page 4 of 4)
common flash interface (cfi) m29w256gh, m29w256gl 86/98 appendix b common flash interface (cfi) the common flash interface is a jedec approved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. the system can interface easily with the device, enabling the software to upgrade itself when necessary. when the read cfi query command is issued, the memory enters read cfi query mode and read operations output the cfi data. table 39 , ta bl e 4 0 , table 41 , table 42 , ta bl e 43 and table 44 show the addresses (a-1, a0-a7) used to retrieve the data. the cfi data structure also contains a security area where a 64-bit unique security number is written (see table 44: security code area ). this area can be accessed only in read mode by the final user. it is impossible to change the security number after it has been written by numonyx. table 39. query structure overview (1) 1. query data are always presented on the lowest order data outputs. address sub-section name description x16 x8 10h 20h cfi query identification string command set id and algorithm data offset 1bh 36h system interface information device timing & voltage information 27h 4eh device geometry definition flash device layout 40h 80h primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) 61h c2h security code area 64-bit unique device number table 40. cfi query identification string (1) 1. query data are always presented on the lowest order data outputs (dq7-dq0) only. dq8-dq15 are ?0?. address data description value x16 x8 10h 20h 0051h ?q? 11h 22h 0052h query unique ascii string ?qry? ?r? 12h 24h 0059h ?y? 13h 26h 0002h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm spansion compatible 14h 28h 0000h 15h 2ah 0040h address for primary algorithm extended query table (see ta ble 4 3 ) p = 40h 16h 2ch 0000h 17h 2eh 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 18h 30h 0000h 19h 32h 0000h address for alternate algorithm extended query table na 1ah 34h 0000h
m29w256gh, m29w256gl common flash interface (cfi) 87/98 table 41. cfi query system interface information (1) address data description value x16 x8 1bh 36h 0027h v cc logic supply minimum program/erase voltage bit 7 to 4bcd value in volts bit 3 to 0bcd value in 100 mv 2.7 v 1ch 38h 0036h v cc logic supply maximum program/erase voltage bit 7 to 4bcd value in volts bit 3 to 0bcd value in 100 mv 3.6 v 1dh 3ah 00b5h v pph [programming] supply minimum program/erase voltage bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 mv 11.5 v 1eh 3ch 00c5h v pph [programming] supply maximum program/erase voltage bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 mv 12.5 v 1fh 3eh 0004h typical timeout for single byte/word program = 2 n s16 s 20h 40h 0004h typical timeout for minimum size write buffer program = 2 n s16 s 21h 42h 0009h typical timeout for individual block erase = 2 n ms 0.5 s 22h 44h 0011h typical timeout for full chip erase = 2 n ms 80 s 23h 46h 0004h maximum timeout for byte/word program = 2 n times typical 200 s 24h 48h 0004h maximum timeout for write buffer program = 2 n times typical 200 s 25h 4ah 0003h maximum timeout per individual block erase = 2 n times typical 2.3 s 26h 4ch 0004h maximum timeout for chip erase = 2 n times typical 800 s 1. the values given in the above table are valid for both packages.
common flash interface (cfi) m29w256gh, m29w256gl 88/98 table 42. device geometry definition address data description value x16 x8 27h 4eh 0019h device size = 2 n in number of bytes 32 mbytes 28h 29h 50h 52h 0002h 0000h flash device interface code description x8, x16 async. 2ah 2bh 54h 56h 0006h 0000h maximum number of bytes in multiple-byte program or page= 2 n 64 2ch 58h 0001h number of erase block regions. it specifies the number of regions containing contiguous erase blocks of the same size. 1 2dh 2eh 5ah 5ch 00ffh 0000h erase block region 1 information number of erase blocks of identical size = 007fh +1 256 2fh 30h 5eh 60h 0000h 0002h erase block region 1 information block size in region 1 = 0200h * 256 byte 128 kbytes 31h 32h 33h 34h 62h 64h 66h 68h 0000h 0000h 0000h 0000h erase block region 2 information 0 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information 0 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information 0
m29w256gh, m29w256gl common flash interface (cfi) 89/98 table 43. primary algorithm-specific extended query table (1) address data description value x16 x8 40h 80h 0050h primary algorithm extended query table unique ascii string ?pri? ?p? 41h 82h 0052h ?r? 42h 84h 0049h ?i? 43h 86h 0031h major version number, ascii ?1? 44h 88h 0033h minor version number, ascii ?3? 45h 8ah 0010h address sensitive unlock (bits 1 to 0) 00 = required, 01= not required silicon revision number (bits 7 to 2) ye s 65 nm 46h 8ch 0002h erase suspend 00 = not supported, 01 = read only, 02 = read and write 2 47h 8eh 0001h block protection 00 = not supported, x = number of blocks per group 1 48h 90h 0000h temporary block unprotect 00 = not supported, 01 = supported not supported 49h 92h 0008h block protect /unprotect 06 = m29w256gh/m29w256gl 6 4ah 94h 0000h simultaneous operations: not supported na 4bh 96h 0000h burst mode, 00 = not supported, 01 = supported not supported 4ch 98h 0002h page mode, 00 = not supported, 02 = 8-word page 02 4dh 9ah 00b5h v pph supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 11.5 v 4eh 9ch 00c5h v pph supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 12.5 v 4fh 9eh 00xxh top/bottom boot block flag xx = 04 = m29w256gl. first block protected by v pp /wp xx = 05 = m29w256gh. last block protected by v pp /wp uniform + v pp /wp protecting highest or lowest block 50h a0h 0001h program suspend, 00 = not supported, 01 = supported supported 1. the values given in the above table are valid for both packages.
common flash interface (cfi) m29w256gh, m29w256gl 90/98 table 44. security code area address data description x16 x8 61h c3h, c2h xxxx 64-bit: unique device number 62h c5h, c4h xxxx 63h c7h, c6h xxxx 64h c9h, c8h xxxx
m29w256gh, m29w256gl extended memory block 91/98 appendix c extended memory block the m29w256gh/l has an extra block, the extended memory block, that can be accessed using a dedicated command. this extended memory block is 128 words in x 16 mode and 256 bytes in x 8 mode. it is used as a security block (to provide a permanent security identification number) or to store additional information. the device can be shipped either with the extended memory block factory locked, or factory unlocked. the extended memory block cannot be erased, and is one-time programmable (otp) memory. if memory block is factory locked or customer protected by setting the extended memory block protection bit, it cannot be further modified. if the extended memory block is not factory locked, it can be customer lockable. its status is indicated by bit dq7 in autoselect mode. this bit is permanently set to either ?1? or ?0? at the factory and cannot be changed. when set to ?1?, it indicates that the device is factory locked and the extended memory block is protected. when set to ?0?, it indicates that the device is customer lockable. bit dq7 being permanently locked to either ?1? or ?0? is another security feature which ensures that a customer lockable device cannot be used instead of a factory locked one. bit dq7 is the most significant bit in the extended memory block verify indicator. it can be read in auto select mode using either the programmer (see ta bl e 8 and table 9 ) or the in- system method (see ta bl e 12 and table 13 ). the extended memory block can only be accessed when the device is in extended memory block mode. for details of how the extended memory block mode is entered and exited, refer to the section 6.4.2: extended memory block and to ta bl e 1 9 and ta bl e 20 . c.1 factory locked extended memory block in devices where the extended memory block is factory locked, the security identification number is written to the extended memory block address space (see table 45: extended memory block address and data ) in the factory. the dq7 bit is set to ?1? and the extended memory block cannot be unprotected.
extended memory block m29w256gh, m29w256gl 92/98 c.2 customer lockable extended memory block a device where the extended memory block is customer lockable is delivered with the dq7 bit set to ?0? and the extended memory block unprotected. it is up to the customer to program and protect the extended memory block but care must be taken because the protection of the extended memory block is not reversible. if the device has not been shipped with the extended memory block factory protected, the block can be protected by setting the extended memory block protection bit, dq0, to ?0?. however, this bit is one-time programmable and once protected the extended memory block cannot be unprotected. once the extended memory block is programmed, the exit extended memory block command must be issued to exit the extended memory block mode and return the device to read mode. table 45. extended memory block address and data address (1) 1. see table 37: block addresses 0 - 127 and table 38: block addresses 128 - 255 . data x8 x16 factory locked customer lockable 000000h-0000ffh 000000h-00007fh security identification number determined by customer
m29w256gh, m29w256gl flowcharts 93/98 appendix d flowcharts figure 29. write to buffer program flowchart and pseudocode 1. n+1 is the number of addresses to be programmed. 2. a write to buffer program abort and reset must be issued to return the device in read mode. 3. when the block address is specified, any address in the selected block address space is acceptable. however when loading write buffer address with data, all addres ses must fall within the selected write buffer page. 4. dq7 must be checked since dq5 and dq7 may change simultaneously. 5. if this flowchart location is reached because dq5=?1?, then the write to buffer program command failed. if this flowchart location is reached because dq1=?1?, th en the write to buffer program command aborted. in both cases, the appropriate reset command must be issued to return the device in read mode: a reset command if the operation failed, a write to buffer program abort and reset command if the operation aborted. 6. see table 12 and table 13 , for details on write to buffer program command sequence. write to buffer command, block address ai08968b start write buffer data, start address yes abort write to buffer fail or abort (5) no write n (1) , block address x = 0 write next data, program address pair x = x-1 write to buffer program confirm, block address read status register (dq1, dq5, dq7) at last loaded address yes dq7 = data no check status register (dq5, dq7) at last loaded address (3) no yes write to a different block address write to buffer and program aborted (2) no dq5 = 1 yes no dq1 = 1 yes yes dq7 = data (4) no end first three cycles of the write to buffer and program command x=n
flowcharts m29w256gh, m29w256gl 94/98 figure 30. enhanced buffered program flowchart and pseudocode 1. an enhanced buffered program abort reset command must be issued to return the device in read mode. enhanced buffered program command set start read dq5 & dq6 at valid address dq6 = toggle dq5 =1 read dq6 twice at valid address dq6 = toggle fail read dq6 at valid address 1 4243_m29256g read status register (dq1, dq5, dq7) at last loaded address dq7 = data check status register (dq5, dq7) at last loaded address dq5 = 1 dq7 = data (3) enhanced buffered program confirm, block address fail or abort (4) 258 th write cycle of the enhanced buffered program command end new program? exit enhanced buffered program command set yes yes yes yes yes yes yes no no no dq1 = 1 yes no no no no no x = x-1 write buffer data, start address (00), x=255 x = 0 no abort write to buffer write next data, (2) program address pair yes write to a different block address enhanced buffered program aborted (1) enhanced buffered program command, block address write next data, (2) program address pair first cycle of the enhanced buffered program command yes no
m29w256gh, m29w256gl flowcharts 95/98 2. when the block address is specified, all the addresses in the selected block address space must be issued starting from (00). furthermore, when loading write buffer address with data, data program addresses must be consecutive. 3. dq7 must be checked since dq5 and dq7 may change simultaneously. 4. if this flowchart location is reached because dq5=?1?, then the enhanced buffered program command failed. if this flowchart location is reached because dq1=?1?, then the enhanced buffered program command aborted. in both cases, the appropriate reset command must be issued to return the devic e in read mode: a reset command if the operation failed, a buffered program abort and reset command if the operation aborted. 5. see table 18: enhanced buffered program commands, 16-bit mode , for details on enhanced buffered program command sequence.
revision history m29w256gh, m29w256gl 96/98 12 revision history table 46. document revision history date version changes 24-nov-2008 01 initial release.
m29w256gh, m29w256gl 97/98 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 2008, numonyx, b.v., all rights reserved.
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